Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract: A method of forming fine patterns of a semiconductor device is provided. The method includes forming plural preliminary first mask patterns, which are spaced apart from each other by a first distance in a direction parallel to a surface of a substrate, on the substrate; forming an acid solution layer on the substrate to cover the plural preliminary first mask patterns; forming plural first mask patterns which are spaced apart from each other by a second distance larger than the first distance, of which upper and side portions are surrounded by acid diffusion regions having first solubility; exposing the first acid diffusion regions by removing the acid solution layer; forming a second mask layer having second solubility lower than the first solubility in spaces between the acid diffusion regions; and forming plural second mask patterns located between the plural first mask patterns, respectively, by removing the acid diffusion regions by the dissolvent.

Abstract: The invention discloses a method (200, 300, 400) for traffic control in a cellular telephony system (100) comprising a number of cells, each cell comprising at least one Radio Base Station, RBS, (170). The system (100) comprises at least one Radio Network Controller, RNC, (110 130 150), for the control of a number of Radio Base stations. The traffic between an RBS and an RNC comprises a number of flows. The invention is intended for the control of flows from the Radio Base Stations to their RNC. The method uses one control function for each flow from each of said Radio Base Stations, and also comprises a congestion detection function (220) which detects the presence or absence of congestion in the traffic from an RBS to an RNC, and which, upon detection of congestion reduces the bit rate of the congested traffic, and in the absence of congestion, increases the bit rate of the previously congested traffic.

Abstract: A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change.

Abstract: MRI-Surgical systems include: (a) at least one MRI-compatible surgical tool; (b) a circuit adapted to communicate with an MRI scanner; and (c) at least one display in communication with the circuit. The circuit electronically recognizes predefined physical characteristics of the at least one tool to automatically segment MR image data provided by the MRI scanner whereby the at least one tool constitutes a point of interface with the system. The circuit is configured to provide a User Interface that defines workflow progression for an MRI-guided surgical procedure and allows a user to select steps in the workflow, and wherein the circuit is configured to generate multi-dimensional visualizations using the predefined data of the at least one tool and data from MRI images of the patient in substantially real time during the surgical procedure.

Abstract: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.

Abstract: A semiconductor device may include an insulating layer and a semiconductor electrode on the insulating layer. An area of increased electrical resistance may separate a contact area of the semiconductor electrode from an active area of the semiconductor electrode. In addition, a metal contact may be provided on the contact area of the semiconductor electrode opposite the insulating layer.

Abstract: Methods, systems, and products are disclosed for specifying a signature for an encrypted packet stream. One method receives the encrypted stream of packets, and encryption obscures the contents of a packet. A signature for insertion into the stream of packets is specified, and the signature identifies a type of data encrypted within the stream of packets. The signature identifies the contents of the packet despite the encryption obscuring the contents.

Abstract: The present invention relates to a method and an arrangement for optimizing radio resource utilizations when scheduling data transmissions between a radio base station (15) and one or more user equipments (18) on a radio channel over a radio interface in a communication network comprising a plurality of said radio base stations (15) serving cells between which said user equipments (18) are moving. Firstly information on channel quality of said radio channel is obtained. Also, information on the traffic per user within the cell is obtained. Then, the information on channel quality and said traffic information are combined and the data transmission is scheduled based on the combination.

Abstract: The invention relates to a method for transmitting call data in a digital wireless communication network, said call data being transmitted over at least one radio frequency channel in a sequence of timeslots. Call data are transmitted in the network using timeslot hopping in which the call data of each user of the network are transmitted with a different timeslot hopping sequence.

Abstract: Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

Abstract: The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise.

Abstract: A multi-layer polarization grating includes a first polarization grating layer, a second polarization grating layer on the first polarization grating layer, and a third polarization grating layer on the second polarization grating layer, such that the second polarization grating layer is between the first and third polarization grating layers. The second polarization grating layer has a periodic molecular structure that is offset relative to that of the first polarization grating layer along an interface therebetween. The third polarization grating layer may also have a periodic molecular structure that is offset relative to that of the second polarization grating layer along an interface therebetween. As such, the periodic molecular structures of the first and second polarization grating layers may be out of phase by a first relative angular shift, and the periodic molecular structures of the second and third polarization grating layers may be out of phase by a second relative angular shift.

Abstract: Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the program verification operation, a target verify voltage is used as a pre-verify voltage. The nonvolatile memory device controls the bit line voltage of the next program loop according to the program verification result, thus making it possible to reduce the threshold voltage distribution of a memory cell. Also, the nonvolatile memory device uses the target verify voltage as the pre-verify voltage, thus making it possible to increase the program verification speed.

Abstract: A hitch apparatus includes a housing configured to be attached to a vehicle, a tow bar movably disposed within the housing, a hitch member assembly, and a fastener configured to removably secure the hitch member assembly to the height adjustment member at any of a plurality of selected elevations. The tow bar is movable relative to the housing between retracted and extended positions, and is pivotable relative to the housing when in an extended position. As such, a hitch member at the distal end of the tow bar has horizontal and vertical adjustment capabilities.

Abstract: A multi-stage amplifier includes a first, a second, and a third sub-amplifier, each with respective input and output ports. The multi-stage amplifier also includes a common output port. The output port of the second sub-amplifier is connected to the output port of the first sub-amplifier as well as to the common output port of the multi-stage amplifier, and the output port of the third sub-amplifier is connected to the common output port. The electrical lengths of the connections from the second sub-amplifier's output port both to the first amplifier's output port and to the common output port are longer or shorter than one quarter of a wavelength (?) of the frequency for which the multi-stage amplifier is intended to operate.

Abstract: A method of packaging a semiconductor device may include providing a semiconductor substrate including first and second spaced apart semiconductor chip areas, and adhering a cover on the first and second spaced apart semiconductor chip areas of the semiconductor substrate. A scribe line may be formed through the semiconductor substrate between the first and second semiconductor chip areas with a semiconductor bridge pattern remaining connected between the first and second spaced apart semiconductor chip areas after forming the scribe line. The cover and the semiconductor bridge pattern may then be cut after forming the scribe line.

Abstract: A method of making a metalloporphyrin is carried out by reacting (i) a linear tetrapyrrole, said linear tetrapyrrole having a 19-acyl group and a 1-protecting group, with (ii) a metal salt under basic conditions to produce the metalloporphyrin. Products produced by such methods and intermediates useful for carrying out such methods are also described.