Abstract: The present invention relates to a method and an arrangement for optimizing radio resource utilizations when scheduling data transmissions between a radio base station (15) and one or more user equipments (18) on a radio channel over a radio interface in a communication network comprising a plurality of said radio base stations (15) serving cells between which said user equipments (18) are moving. Firstly information on channel quality of said radio channel is obtained. Also, information on the traffic per user within the cell is obtained. Then, the information on channel quality and said traffic information are combined and the data transmission is scheduled based on the combination.

Abstract: The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise.

Abstract: The invention relates to a method for transmitting call data in a digital wireless communication network, said call data being transmitted over at least one radio frequency channel in a sequence of timeslots. Call data are transmitted in the network using timeslot hopping in which the call data of each user of the network are transmitted with a different timeslot hopping sequence.

Abstract: A multi-layer polarization grating includes a first polarization grating layer, a second polarization grating layer on the first polarization grating layer, and a third polarization grating layer on the second polarization grating layer, such that the second polarization grating layer is between the first and third polarization grating layers. The second polarization grating layer has a periodic molecular structure that is offset relative to that of the first polarization grating layer along an interface therebetween. The third polarization grating layer may also have a periodic molecular structure that is offset relative to that of the second polarization grating layer along an interface therebetween. As such, the periodic molecular structures of the first and second polarization grating layers may be out of phase by a first relative angular shift, and the periodic molecular structures of the second and third polarization grating layers may be out of phase by a second relative angular shift.

Abstract: Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.

Abstract: Faults are detected and recovered from in a multiprotocol label switching (MPLS) network by communicating packets between a first node and a second node in the MPLS network using a set of prioritized label switch path (LSP) pairs. A failure to receive a relatively constant rate of packets during a predetermined time interval is detected at the first node. Packets are sent from the first node to the second node using a backup LSP pair responsive to detecting the failure. Packets are then sent from the second node to the first node using a backup LSP pair responsive to receiving packets at the second node on the backup LSP pair.

Abstract: Photosensor circuits include a relay coil configured to control application of an alternating current (AC) power source to a load. The circuit includes a pulse width modulator circuit configured to generate a pulse width modulated signal having a pulse width that varies responsive to an average voltage across the relay coil, including a capacitor of an averaging circuit coupled in parallel with the relay coil. A drive transistor is coupled between the relay coil and a neutral bus that controls the average voltage across the relay coil responsive to the pulse width modulated signal. A photo control circuit, including a select transistor, is configured to control application of the pulse width modulated signal to the drive transistor responsive to a detected light level. The pulse width modulator circuit further includes a current amplifier coupled between the voltage averaging circuit and the select transistor.

Abstract: A method of making a metalloporphyrin is carried out by reacting (i) a linear tetrapyrrole, said linear tetrapyrrole having a 19-acyl group and a 1-protecting group, with (ii) a metal salt under basic conditions to produce the metalloporphyrin. Products produced by such methods and intermediates useful for carrying out such methods are also described.

Abstract: A domestic appliance for built-in installation, comprising: a housing having at least two sides; a front door; a hinge mechanism, provided at or adjacent one of the sides, coupling the door to the housing and permitting relative movement thereof, wherein the door is movable between a first position, in which the door is closed, and a second position, in which the door is fully open; and/or wherein the hinge is so shaped and dimensioned whereby, in use, the extent of protrusion of the door laterally beyond said one side when the door is in said second position is less than or equal to that when the door is in said first position. Preferably, the hinge mechanism is shaped and arranged whereby double movement, for example both rotational and translational movement, of the door relative to the housing is facilitated during movement between said first position and said second position.

Abstract: Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

Abstract: A multi-stage amplifier includes a first, a second, and a third sub-amplifier, each with respective input and output ports. The multi-stage amplifier also includes a common output port. The output port of the second sub-amplifier is connected to the output port of the first sub-amplifier as well as to the common output port of the multi-stage amplifier, and the output port of the third sub-amplifier is connected to the common output port. The electrical lengths of the connections from the second sub-amplifier's output port both to the first amplifier's output port and to the common output port are longer or shorter than one quarter of a wavelength (?) of the frequency for which the multi-stage amplifier is intended to operate.

Abstract: A method of packaging a semiconductor device may include providing a semiconductor substrate including first and second spaced apart semiconductor chip areas, and adhering a cover on the first and second spaced apart semiconductor chip areas of the semiconductor substrate. A scribe line may be formed through the semiconductor substrate between the first and second semiconductor chip areas with a semiconductor bridge pattern remaining connected between the first and second spaced apart semiconductor chip areas after forming the scribe line. The cover and the semiconductor bridge pattern may then be cut after forming the scribe line.

Abstract: A hitch apparatus includes a housing configured to be attached to a vehicle, a tow bar movably disposed within the housing, a hitch member assembly, and a fastener configured to removably secure the hitch member assembly to the height adjustment member at any of a plurality of selected elevations. The tow bar is movable relative to the housing between retracted and extended positions, and is pivotable relative to the housing when in an extended position. As such, a hitch member at the distal end of the tow bar has horizontal and vertical adjustment capabilities.

Abstract: Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the program verification operation, a target verify voltage is used as a pre-verify voltage. The nonvolatile memory device controls the bit line voltage of the next program loop according to the program verification result, thus making it possible to reduce the threshold voltage distribution of a memory cell. Also, the nonvolatile memory device uses the target verify voltage as the pre-verify voltage, thus making it possible to increase the program verification speed.

Abstract: Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.

Abstract: A controller may include a RAID controller and an access controller. The RAID controller exchanges data with a host and select ones of a plurality of RAID levels responsive to RAID level information. The access controller is connected to the RAID controller and to a plurality of channels that are each connected to a plurality of non-volatile memory chips. The access controller accesses data in at least one of the non-volatile memory chips connected to each of the channels according to the selected RAID level. The controller may alternatively or additionally include a storage device and a main processor. The main processor is configured to logically partition a plurality of non-volatile memory chips that are connected to each of a plurality of channels into a normal partition region and a RAID level partition region, where data access is performed according to a selected RAID level, in response partition information that is stored in the storage device.

Abstract: An electronic device may include a substrate and an acoustic actuator mounted on a surface of the substrate. More particularly, the acoustic actuator may be configured to generate displacements along a direction parallel with respect to the surface of the substrate in response to an electrical signal applied thereto. A speaker box may define an acoustic volume, and the speaker box may include a speaker box wall with a speaker box opening therethrough adjacent the acoustic actuator. A speaker membrane may be provided across the speaker box opening adjacent the acoustic actuator, and the speaker membrane may be mechanically coupled to the acoustic actuator so that the speaker membrane is configured to deflect responsive to displacements generated by the acoustic actuator. Related methods are also discussed.

Abstract: According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.

Abstract: Disclosed are optimized keratin preparations for use in medical applications. Methods to produce optimized keratin preparations are provided for use in biomedical applications, particularly for the treatment of bleeding, and for the treatment of wounds. Also disclosed are surgical or paramedic aids comprising a substrate with keratin preparations provided thereon, and kits comprising keratin derivatives packaged in sterile form.

Abstract: A communications patching system includes first and second patch panels, each having a plurality of connector ports, and a patch cord that is configured to selectively interconnect a connector port in the first patch panel with a connector port in the second patch panel. Each patch panel includes a port identification circuit that is electrically coupled with the connector ports of the respective patch panel. The port identification circuit of each patch panel is configured to transmit a signal to a connector port of the other patch panel over a common mode transmission path of the patch cord. The first and second connector ports connected by the patch cord are identified from the signal path.