Abstract: A login process is provided in which input to a client computer effects operations by a server computer, comprising the steps of: providing a stream-head in client kernel memory space between a shell program in client user memory space and a terminal-connection module in client kernel memory space; creating a target module in client kernel memory space which includes a network-connection to the server computer, and inserting a source module beneath the stream-head in client kernel memory space which passes information between the terminal-connection module and the target module.

Abstract: Arrangement for lifting image of checks, with Xenon lamp, Fluorescent lamp or like source of stable-wavelength-output and CCPD Camera means selected to exhibit “close-to-human” spectral response plus a photopic filter, disposed upstream of the Camera and adapted to shift its received image-light spectrum in the direction of that which is optimal for the human-eye.

Abstract: In a document processing array, an imaging/illumination arrangement for illuminating and imaging the documents at one or several imaging-sites as they are rapidly transported there-past, each site having, as its illumination source, a hollow Lambertian integrating cylinder housing lamps which project essentially all their light onto the inner cylinder walls to be reflected/diffused thereby in Lambertian fashion and sent to the imaging site(s).

Abstract: An integrated circuit chip having improved on-chip circuitry including a phase-locked-loop for providing accurately timed signal having different durations and differently occurring timing edges.

Abstract: The present invention relates to a method and apparatus for performing decoding of variable length data. It is particularly effective when decoding data encoded with a Huffman or such similar encoding method. The invention employs a plurality of decoding tables which permits a fixed length of bits to be decoded in a minimum number of indexes for the size of the index. Each table is constructed such that the given node indicates whether a unique character has been decoded or whether further decoding is necessary.For data which is encoded in a manner similar to a Huffman code, a properly constructed table will yield the frequently used characters on a single index. Only less frequently used characters require multiple indexes into the plurality of tables.

Abstract: A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals, for better avoiding metastability.

Abstract: An image-based transaction processing system which captures and stores images of debit and credit transaction documents, while also extracting document data for storage in a computer data base. The computer processes the extracted document data to identify out-of-balance transactions. The document images of an out-of-balance transaction are sent to a balancing workstation which provides a multi-window display for controllably displaying the transaction in a manner which permits the cause of the out-of-balance condition to be readily determined and corrected. The multi-window display includes windows for displaying selected images of debit and credit documents as well as windows for displaying credit and debit amounts and the out-of-balance amount of the transaction.

Abstract: An I/O system where there is provided a Task Control Processor which provides for the scheduling of the different central processors for the highest priority processes to be run. When an initiate I/O operation is detected, the respective processor is released from the process that it is currently running and can be assigned to the next highest priority process. When the requested I/O operation has been completed, the Task Control Processor is signalled so that the Task Control Processor can put the requesting process back into the priority list of processes to be run by the main central processors.

Abstract: A method for separating integer and fractional portions of a financial amount preparatory to recognition of the financial amount. This separating is accomplished based on determining the presence of at least one of a plurality of possible distinguishing separation characteristics, such as the presence of a period (decimal point), superscripted characters, or a fraction. The separated fractional portion is then categorized into one of a plurality of categories based on the nature of the fractional portion representation. The characters making up this fractional portion are then extracted based on this categorizing.

Abstract: An image-based document processing system comprised of a plurality of hardware components arranged as a platform for processing documents using document images. The system employs a layered software architecture comprised of application programs, system services and a plurality of native operating systems provided for particular ones of the hardware components. The system services are callable by the application programs to provide an interface between the application programs and the native operating systems during operation of the system.

Abstract: High speed instruction execution apparatus is disclosed which provides multistage pipelining and branch prediction in a manner which permits speculative changes of state to be made during execution of a predicted instruction before the correctness of the prediction has been determined.

Abstract: An IC chip employs a common multiplexor logic element in different logic configurations for performing a variety of different logic functions, whereby path delays can be accurately matched. In addition, a phase-locked-loop is employed for providing accurately timed signals having different durations and differently occurring timing edges.

Abstract: A CTOS network comprised of a plurality of workstations provides for virtual demand paging transparently across the network in a manner which permits a large virtual memory to efficiently be provided for each of a plurality of concurrently running applications on a CTOS workstation. Each application running on the workstation is provided with assigned pages and a local clock which operates based on the well known clock algorithm. A unique combination of local policy and global policy is used for page replacement which results in significantly more efficient management of available memory pages. The global policy includes an "elbow room" enhancement which permits the global page replacement policy to better take into account the individual activity of the concurrently running applications. In addition, enhanced prefaulting and page cleaning are provided, whereby it is made significantly more likely that a running application will find a requested page in its local clock.

Abstract: A Wallace-type binary tree multiplier in which the partial products of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels comprised of full and half adders. This reduction continues until a final set of inputs is produced wherein no more than two inputs remain to be added in any column. This final set is then added using a serial adder and a carry lookahead adder to produce the desired product. The additions at each level are performed in accordance with prescribed rules to provide for fastest overall operating speed and minimum required chip area. In addition, the lengths of the serial adder and carry lookahead adder are chosen to further enhance speed while reducing required chip area. A still further enhancement in multiplier operating speed is achieved by providing connections to adders so as to take advantage of the different times of arrival of the inputs to each level along with different adder input-to-output delays.

Abstract: An integrated circuit chip on which a relatively large on-chip delay is provided using a relatively small delay in conjunction with a phase-locked-loop, whereby the relatively large variations typical of large on-chip delays are avoided.

Abstract: A method for enhancing the performance of an artificially intelligent system employing a neural network by proving an optimized training set for training the neural network. The optimized training set is produced by identifying and removing inaccurate training pairs in the training set.

Abstract: A method for enhancing the performance of an artificially intelligent system employing a neural network by proving an optimized training set for training the neural network. The optimized training set is produced by identifying and permanently removing inaccurate training pairs in the training set. The permanent removal of inaccurate training pairs is performed in a worst-error order.

Abstract: An image-based transaction processing system employing automatic reading of machine-printed and handwritten financial amounts on transaction documents to enhance transaction balancing by reducing the number of transactions which have to be balanced by an operator. The automatic reader provides a second choice as well as a first choice for one or more digits. When an out-of-balance transaction is detected, one or more second choice digits are substituted for corresponding first choice digits in order to obtain automatic transaction balancing even through an automatically read amount is incorrect.

Abstract: Method and apparatus for writing data to files from a computer system to a Write Once Read Many (WORM) Disc medium which results in a creation of an ISO 9660 standard disc is disclosed. The method and apparatus each efficiently manages writes to WORM medium in the creation of a file structure that conforms to ISO standard 9660 which governs management of CD-ROM disc files. The method and apparatus are efficient both in terms of the time required to perform such writes and in the amount of medium consumed as overhead. In addition, the invention provides a method and apparatus for writing to WORM disc in which there is a high degree of confidence that the information written is indelible.

Abstract: An improved input/output subsystem allowing data transfers between the input/output subsystem and an input/output controller along a subsystem input/output bus to occur at a data transfer rate established by the transfer rate of the processor bus connected between the input/output controller and the central processing unit. Data is transferred from an electronic memory within the input/output subsystem to data buffers within the input/output controller via a direct memory access.