Patents Represented by Attorney Nathan Cass

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  • Method for providing automatic clock de-skewing on a circuit board
    Patent number: 4754164
    Abstract: A method of providing automatic clock de-skewing for integrated circuit chips carried by a multi-layer circuit board. In a preferred implementation of the method, a clock distribution chip includes on-chip automatic clock de-skewing circuitry requiring an accurate reference delay which is advantageously provided by a strip transmission line formed on one of the conductive planes of the multi-layer circuit board containing the chips.
    Type: Grant
    Filed: June 30, 1984
    Date of Patent: June 28, 1988
    Assignee: Unisys Corp.
    Inventors: Laurence P. Flora, Michael A. McCullough
  • Printer-tape data link processor with DMA slave controller which automatically switches between dual output control data chomels
    Patent number: 4750107
    Abstract: A peripheral controller (data link processor) controls data transfers between a host computer and a plurality of tape peripheral units and a single printer peripheral unit. A master microprocessor commands three subordinate controllers to permit concurrent data transfers through a buffer memory in both the Read and the Write directions. A dual channel control from the master microprocessor actuates a DMA switch so that data transfers to/from the tape units can be controlled by switching on alternate control lines which regulate the data transfer operations.
    Type: Grant
    Filed: January 7, 1985
    Date of Patent: June 7, 1988
    Assignee: Unisys Corporation
    Inventor: Jerrold E. Buggert
  • Dual function I/O controller
    Patent number: 4750113
    Abstract: An I/O controller functions to provide management of, control of, while functioning as two "virtual" data link processors for at least two separate types of peripheral terminal units, thus enabling data transfers between a host computer and any selected one of the peripheral terminal units. A commonly shared logic interface, common to both virtual controllers, is selected for use by a Request-Program Array Logic unit which arbitrates the utilization of the common logic by one of two virtual controllers at any given time. A first and second status latch is provided in the common front end interface of the I/O controller whereby each status latch provides status signals to the main host computer system of the state of any one of two virtual controllers which share common interface to a host computer.
    Type: Grant
    Filed: February 28, 1985
    Date of Patent: June 7, 1988
    Assignee: Unisys Corporation
    Inventor: Jerrold E. Buggert
  • Data transfer system using two peripheral controllers to access dual-ported data storage units
    Patent number: 4747047
    Abstract: A data transfer network includes a group of disk drive peripheral units, each has dual ports for connection to two separate peripheral-controllers. A host computer can initiate either peripheral-controller to access selected disk drive units for Read/Write operations.
    Type: Grant
    Filed: December 6, 1985
    Date of Patent: May 24, 1988
    Assignee: Unisys Corporation
    Inventors: Ronald S. Coogan, Toan D. Dang
  • IC chip error detecting and correcting method
    Patent number: 4739504
    Abstract: A method employing two identical IC chips for providing error detecting and correcting operations on a plurality of input bits comprised of input data bits and input check bits, wherein a single one of the IC chips has an insufficient number of available outputs to provide all of the required outputs. The method includes applying the input data bits and the input check bits to the input terminals of each IC chip in an inverse manner relative to one another, and then performing the error detecting and correcting operations on each chip in accordance with an inversely symmetrical Hamming code. As a result, even though the same detecting and correcting operations are performed on each IC chip, they are performed in an inverse manner with respect to the input data and input check bits so that each IC chip is able to provide one-half of the required output bits.
    Type: Grant
    Filed: June 3, 1985
    Date of Patent: April 19, 1988
    Assignee: Unisys Corp.
    Inventor: Duane W. Leslie
  • IC chip error detecting and correcting apparatus
    Patent number: 4739506
    Abstract: Error detecting and correcting operations for a plurality of input bits comprised of input data bits and associated check bits are implemented using two IC chips in order to overcome chip output limitations. The use of two identical IC chips for this purpose is made possible by employing a specially chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.
    Type: Grant
    Filed: June 3, 1985
    Date of Patent: April 19, 1988
    Assignee: Unisys Corp.
    Inventor: Duane W. Leslie
  • IC chip error detecting and correcting apparatus with automatic self-checking of chip operation
    Patent number: 4739505
    Abstract: Error detecting and correcting operations for a plurality of input bits comprised of input data bits and associated check bits are implemented using two IC chips in order to overcome chip output limitations. In addition, redundancies derived from the use of two IC chips are employed to provide automatic self-checking of the detecting operation of each chip. The use of two identical IC chips for this purpose is made possible by employing a specially chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: April 19, 1988
    Assignee: Unisys Corp.
    Inventor: Duane W. Leslie
  • Air seal retention means
    Patent number: 4736274
    Abstract: Disclosed are air seals adapted to be so engaged in a receiving card rack slot as to thrust out against the opposed slot bases and thus establish "base-engaging" retention forces, this effected in some embodiments by forming a base-engaging flexure strip along each tongue of the seal to that, despite dimensional and other variations, each flexure strip will be thrust-away somewhat from its slot-forming channel, when the seal is firmly seated in a slot.
    Type: Grant
    Filed: December 22, 1986
    Date of Patent: April 5, 1988
    Assignee: Unisys Corp.
    Inventors: Michael L. Davies, Lawrence Weber
  • Heat sink device assembly for encumbered IC package
    Patent number: 4733293
    Abstract: A heat sink device assembly providing a radially finned heat sink with a tapered base is provided for application to surface-encumbered integrated circuit packages for heat dissipation purposes. The device involves a patterned set of radial fin elements, through which cooling air flow may pass, mounted on a baseplate. A taper or reduction in cross sectional area of the baseplate is provided in order to maximize the surface area for heat dissipation while constraining the area of attachment, thus avoiding physical or electrical contact with peripheral objects or areas placed on the surface edges of the integrated circuit package.
    Type: Grant
    Filed: February 13, 1987
    Date of Patent: March 22, 1988
    Assignee: Unisys Corporation
    Inventor: Paul G. Gabuzda
  • System for selecting best fit vector code in vector quantization encoding
    Patent number: 4727354
    Abstract: A system and apparatus for encoding a set of input vector components by initiating a sequential search through a codebook memory to put out a series of associated error code vectors which can be compared in sequence over a period of time in order to select the minimum error code vector (best fit). A clocking-sequencing means enables an output latch to hold (after termination of the sequence period) the index number which represents the particular error code vector presently having the minimum distortion. Each new set of input vector components will be sequenced to search for the minimum error code vector (and index) for that particular set of input vector components.
    Type: Grant
    Filed: January 7, 1987
    Date of Patent: February 23, 1988
    Assignee: Unisys Corporation
    Inventor: Robert A. Lindsay
  • IC chip error detecting and correcting method including automatic self-checking of chip operation
    Patent number: 4723245
    Abstract: A method employing two identical IC chips for providing error detecting and correcting operations on a plurality of input bits comprised of input data bits and input check bits, wherein a single one of the IC chips has an insufficient number of available outputs to provide all of the required outputs. The method includes applying the input data bits and the input check bits to the input terminals of each IC chip in an inverse manner relative to one another, and then performing the error detecting and correcting operations on each chip in accordance with an inversely symmetrical Hamming code. In addition, by taking advantage of redundancies in the performance of error detecting operations, the method also provides for automatic self-checking of chip operations.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: February 2, 1988
    Assignee: Unisys Corporation
    Inventor: Duane W. Leslie
  • High capacity disk storage system having unusually high fault tolerance level and bandpass
    Patent number: 4722085
    Abstract: A relatively large plurality of relatively small, independently operating disk subsystems are coupled to a read/write interface containing error circuitry and data organizer circuitry. The data organizer circuitry organizes read/write data for read/write communication with the disk subsystems via the error circuitry such that the overall system appears as a large, high capacity disk system having an unusually high fault tolerance and a very high bandpass.
    Type: Grant
    Filed: February 3, 1986
    Date of Patent: January 26, 1988
    Assignee: Unisys Corp.
    Inventors: Laurence P. Flora, Gary V. Ruby
  • Wave solder finger shield apparatus
    Patent number: 4717064
    Abstract: A set of titanium guide bars are shaped with inner angular finger shields to isolate designated underside edge areas of a printed circuit board being conveyed across a molten solder bath in a wave solder machine.
    Type: Grant
    Filed: August 15, 1986
    Date of Patent: January 5, 1988
    Assignee: Unisys Corporation
    Inventors: Edward J. Popielarski, Kenneth D. Thomas
  • Preparation of magnetic coating
    Patent number: 4717493
    Abstract: A magnetic coating composition is disclosed of the type having magnetic particles dispersed in a resin binder. The improvement comprises the use of a solvent system including a dibasic ester wherein the solvent system has an initial Hansen three-dimensional solubility parameter range of approximately 10.5 to 11.0 and a Hansen three-dimensional solubility parameter range of approximately 9.3 to 10.0 after approximately 99% of the solvent has been evaporated from the binder.
    Type: Grant
    Filed: October 3, 1986
    Date of Patent: January 5, 1988
    Assignee: Unisys Corporation
    Inventors: Duncan W. Frew, Zorro Stefanini, Edward A. Schnee, Leo di Ricco
  • Staggered radial-fin heat sink device for integrated circuit package
    Patent number: 4715438
    Abstract: A radial fin heat sink whereby a spreader plate supports a series of radial fins which are staggered around a central open cylindrical area designed to receive a flow of air by impingement. The radial fins comprise a pattern of variable lengths which follow in succession from a major length to a minor length to an intermediate length which pattern repeats around the periphery of the spreader plate.
    Type: Grant
    Filed: June 30, 1986
    Date of Patent: December 29, 1987
    Assignee: Unisys Corporation
    Inventors: Paul G. Gabuzda, Sanford V. Terrell
  • Means and methods for improved transducing of flexible disk packs
    Patent number: 4713705
    Abstract: Improved transducing techniques and arrangements; the embodiments particularly adapted for co-action with disk drive apparatus for handling flexible disk packs, and including a partitioning shield, flexure-bar mounted transducer head under the shield, along with disk-cleaner/stabilizer means--especially where these are arrayed in the form of a double-opposed transducer assembly adapted to be so manipulated into the pack as to double-partition the pack away from a selected disk on which opposed dual-transducing operations may be carried out.Such arrangements eliminate the need for separate pressure-pads, incorporating them on opposed-heads adapted to transduce on both sides of a record mounted on the ends of respective pivotable flexure-bars. Such cleaner/stabilizers can be opposed, engaged an intermediate record, squeezingly.
    Type: Grant
    Filed: June 18, 1981
    Date of Patent: December 15, 1987
    Assignee: Unisys Corp.
    Inventors: Dean DeMoss, Herbert U. Ragle
  • Parity detection system for wide bus circuitry
    Patent number: 4710935
    Abstract: A parity checking system for establishing integrity of data transfer on a wide bus. Each set of "4" bus lines of a multiple line bus is passed from a driver chip to a corresponding receiver chip. An added parity driver chip senses each corresponding bit line of each driver chip to develop a set of four parity signals for comparison with corresponding parity signals from each corresponding bit line of each one of a set of receiver chips. Any discrepancy will generate a parity error signal.
    Type: Grant
    Filed: April 4, 1986
    Date of Patent: December 1, 1987
    Assignee: Unisys Corporation
    Inventors: Dongsung R. Kim, Reinhard K. Kronies
  • Float lapping fixture
    Patent number: 4707948
    Abstract: Described is a technique and associated fixture for lapping magnetic recording heads in a group such that each head is mounted on a "free floating" part in the fixture, being biased for lapping only by the weight of this part and being individually removable during lapping mode; and also characterized by capability for pivoting the fixture to change the lap-angle of all such heads in common to a new constant prescribed angle, the parts also being selectibly kept non-rotatable in the fixture.
    Type: Grant
    Filed: November 27, 1981
    Date of Patent: November 24, 1987
    Assignee: Unisys Corp.
    Inventors: Abbott M. Schindler, Otto Fuchs
  • Spacer means on floppy disks and associated techniques
    Patent number: 4707752
    Abstract: Improved spacer means for flexible magnetic disk pack storage systems are illustrated in the embodiments, each preferably comprising a set of fingers arrayed on each disk.
    Type: Grant
    Filed: December 2, 1982
    Date of Patent: November 17, 1987
    Assignee: Unisys Corp.
    Inventor: Ko K. Gyi
  • Flexible access connector with miniature slotted pads
    Patent number: 4703984
    Abstract: A flexible thin film provides interior miniature conducting contact pads which mesh with the extension pins of a pin grid array to establish a tensioned reliable electrical contact. These contacts each connect to an exterior point which is available for probing even while the pin grid array is inserted in a printed circuit board.
    Type: Grant
    Filed: October 28, 1985
    Date of Patent: November 3, 1987
    Assignee: Burroughs Corporation
    Inventor: John W. Mitchell, Jr.