Abstract: Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.

Abstract: A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.

Abstract: A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the return address. The method retrieves the return address from the link stack, in response to both the instruction and the branch instruction being identified and fetches instructions using the return address.

Abstract: The present invention provides a method and apparatus for optimizing the transmission of video configuration data in a system comprising a host computer and a display monitor. The invention comprises a wireless video source adapter connected to the host computer and a wireless video sink adapter connected to the monitor. Upon system startup, the video sink adapter acquires EDID information from the monitor and transmits it to the video source adapter, which does not activate its connection and indicate its presence to the host computer until after receiving the EDID information. The video source adapter then supplies the EDID information to the host computer in response to EDID requests from the computer. In this manner, the video source adapter acts as a virtual proxy for the display monitor from the point of the view of the host computer. The host computer then uses the EDID information to configure its video signal to match the parameters of the display monitor.

Abstract: Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.

Abstract: A circuit having a local power block for leakage reduction is disclosed. The circuit has a first portion and a second portion. The first portion is configured to operate at a substantially greater operating frequency than the operating frequency of the second portion. The second portion has a local power block configured to decouple the second portion if the second portion is inactive to reduce leakage current associated with the second portion without sacrificing performance of the first portion.

Abstract: A current sensing mechanism for use in an integrated circuit is described. In one embodiment, the integrated circuit comprises a voltage supply rail and a current sensor coupled to that voltage supply rail such that the current sensor determines the current passing through the voltage supply rail. Leads attached to the current sensor can be monitored to obtain measurements that permit determination of the current.

Abstract: A system, method and computer-readable medium for reducing the required throughput in an ultra-wideband system is provided. A temporal sub-sampling routine limits the number of frames, or portions thereof, to be transmitted to a sink over an RF link. The temporal sub-sampling routine may have a fixed, or static, sub-sampling rate that specifies the rate at which frames are discarded. In accordance with another embodiment, an automatic temporal sub-sampling mechanism is provided. Additionally, a tile copying mechanism may be implemented for reducing the throughput of the RF link. A WDV subsystem may include an interface to an external frame buffer that facilitates the temporal sub-sampling and tile copy routines disclosed herein.

Abstract: A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.

Abstract: Systems and techniques for adaptive interference filtering in a communications device are disclosed. The communications device may include a transmitter, a receiver, a duplexer coupled to the transmitter and the receiver, and an adaptive filter disposed between the duplexer and the receiver. A processor may be configured to monitor cross modulation in the receiver between transmitter leakage through the duplexer and a jammer, and adapt the filter to vary its transmit signal rejection as a function of the cross modulation.

Abstract: The present invention provides a method for enabling side channel communication between wireless devices. In one embodiment of the invention the guard tones in wireless OFDM signals are used for side channel communication. In another embodiment of the invention, unused bits in OFDM symbols are used as side channels instead of being padded with zeros or random bits.

Abstract: Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.

Abstract: Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.

Abstract: A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.

Abstract: A method for line-based video rate control is provided. The line based video rate control method includes system feedback to change system operating parameters, including on a packet-by-packet basis and also on a line-by-line basis. Also provided is a method for line-based compression. The method includes basic elements of an arithmetic coder to improve Golomb coding performance. By inverting operations in the method for line-based compression, the corresponding decoder can be obtained. The method also provides a heuristic-driven method for generating prediction residuals from quantized data, wherein prediction is driven in the direction of maximum correlation so that it is unnecessary to supply the decoder with additional data specifying this direction at each array element.

Abstract: The convenience of a wireless network is tempered by the concern that a rogue device can listen in on the wireless communications. Determining the position of the home device and other devices within range allows the user of the home device to choose the specific wireless devices with which to communicate. The distance to the other devices within wireless communications range is helpful and allows the user to sort between safe and unsafe or rogue devices. Distance can be determined by a variety of methods including use of trusted references, signal strength, and error rate. Once the safe device is selected, the system will then establish a communications path with that device.

Abstract: A method for precise transmit power adjustment in a wide personal area network (WPAN) is provided that includes coarse adjusting a power level of the radio signal by adjusting a gain setting of an amplifier that is used to power the radio signal, and fine adjusting the power level of the radio signal by adjusting a voltage level of an information signal that is provided to the amplifier so that the power level of the radio signal approaches a maximum allowable power level.

Abstract: Reduction of line delay is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, the bit lines are segmented using latch repeaters to control the bit line length for address selection. The latch repeaters are, in one embodiment, allowed to remain in their operated/non-operated state at the completion of a memory read/write cycle. This then avoids successive enabling pulses when the same segment is accessed on successive cycles.

Abstract: In a particular illustrative embodiment, a system is disclosed that includes a first power domain that is responsive to a first power switching circuit and a second power domain that is responsive to a second power switching circuit. The system also includes a logic circuit adapted to selectively activate the first power switching circuit and the second power switching circuit. At least one of the first power switching circuit and the second power switching circuit includes a first set of transistors adapted for activation during a first power up stage and a second set of transistors adapted for activation during a second power up stage after at least one of the first set of transistors are activated.

Abstract: A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.