Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.

Abstract: A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to shift and round data within a source register unit of a register file structure is received within a processing unit. The instruction includes a shifting bit value indicating the bit amount for a right shift operation and is subsequently executed to shift data within the source register unit to the right by an encoded bit value, calculated by subtracting a single bit from the shifting bit value contained within the instruction. A predetermined bit extension is further inserted within the vacated bit positions adjacent to the shifted data. Subsequently, an addition operation is performed on the shifted data and a unitary integer value is added to the shifted data to obtain resulting data.

Abstract: A Content-Terminated Direct Memory Access (CT-DMA) circuit autonomously transfers data of an unknown length from a source to a destination, terminating the transfer based on the content of the data. Filter criteria are provided to the CT-DMA prior to the data transfer. The filter criteria include pattern data that are compared to transfer data, and transfer termination rules for interpreting the comparison results. Data are written to the destination until the filter criteria are met. Representative filter criteria may include that one or more units of transfer data match pattern data; that one or more units of transfer data fail to match pattern data; or that one or more units of transfer data match pattern data a predetermined number of times.

Abstract: A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.

Abstract: A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.

Abstract: An apparatus comprising plurality of functional integrated circuit blocks, each manufactured with different oxide thicknesses on a monolithic integrated circuit die, is described. Using different gate oxide thicknesses for different functional integrated circuit blocks provides reduced power consumption and increases performance in processing systems. Several embodiments comprising different combinations of functional integrated circuit blocks, including processor cores and memory elements, are presented.

Abstract: A system and method taught herein control data prefetching for a data cache by tracking prefetch hits and overall hits for the data cache. Data prefetching for the data cache is disabled based on the tracking of prefetch hits and data prefetching is enabled for the data cache based on the tracking of overall hits. For example, in one or more embodiments, a cache controller is configured to track a prefetch hit rate reflecting the percentage of hits on the data cache that involve prefetched data lines and disable data prefetching if the prefetch hit rate falls below a defined threshold. The cache controller also tracks an overall hit rate reflecting the overall percentage of data cache hits (versus misses) and enables data prefetching if the overall hit rate falls below a defined threshold.

Abstract: A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.

Abstract: In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalized the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the addend forced to zero. This preserves the value of the product, while normalizing or denormalizing the product using the floating-point adder's normalization circuit. When the operands to the multiply operation are available, they are inspected. If the operands will not generate an unnormal intermediate product or a denormal final product, the add operation is suppressed, such as by operand-forwarding. Additionally, each non-fused floating-point multiply-add instruction is replaced with a multiply-add instruction having a zero addend, and a floating-point add instruction having the addend of the original multiply-add instruction is inserted into the instruction stream.

Abstract: In a particular embodiment, a method is disclosed that includes executing a single instruction to identify a location within a table stored at a memory. The single instruction is executable by a processor to extract bit field data from a first register and insert the bit field data into an index portion of a second register. The second register includes a table address portion and an index portion. The table address portion includes a table address identifying a memory location associated with a table. The table address and the bit field data combine to form an indexed address to an element within the table.

Abstract: Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.

Abstract: A data transmitter (10) divides incoming data for transmission into data blocks and passes them in frame transmission order to a radio link stage (16) via a serial frame buffer (14). The buffer (14) holds the data frames until the radio link stage (16) is able to transmit them. The incoming data has associated with it various parameters. The radio link stage (16) has allocated to it radio link resources. The parameters and resources, which change independently of each other from time to time, are supplied to a controller (18) which calculates high and low buffer levels therefrom. The controller (18) controls the passing of the data frames through the frame buffer (14) to maintain the number of frames in the buffer at any instant of time at a level between the calculated high and low levels.

Abstract: An amplifier comprises a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance.

Abstract: A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.

Abstract: A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

Abstract: Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.

Abstract: Power reduction is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, the bit lines are segmented using latch repeaters to control address selection with respect to segments beyond a first segment. The latch repeaters are, in one embodiment, allowed to remain in their operated/non-operated state at the completion of a memory read/write cycle. This then avoids successive enabling pulses when the same segment is accessed on successive cycles.

Abstract: A transmitter circuit 10 with a first characteristic controllable by a first control signal and a second characteristic controllable by a second control signal is calibrated using a calibration method to enable accurate power control. The transmitter circuit 10 will typically comprise a VGA amplifier 16 and a power amplifier 22. Typically, the gain of the VGA amplifier 16 is controlled and so is the current supplied to the power amplifier 22. The method comprises a number of operations including defining a set of multiple signal values for the first control signal, setting the first control signal to a level corresponding to a signal value from the set of multiple first control signal values. Then the second control signal is adjusted to cause the transmitter to operate in a desired manner and the power in a signal transmitted by the transmitter is measured. The setting, adjusting and measuring is repeated for each signal value in the set of multiple first control signal values.

Abstract: A method of manufacturing a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, depositing a conductive terminal within the trench, and depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a configurable magnetic orientation. The fixed magnetic layer is coupled to the conductive terminal along an interface that extends substantially normal to a surface of the substrate. The free magnetic layer that is adjacent to the conductive terminal carries a magnetic domain adapted to store a digital value.

Abstract: A weakly-ordered processing system implements an execution synchronization bus transaction, or “memory barrier” bus transaction, to enforce strongly-ordered data transfer bus transactions. A slave device that ensures global observability may “opt out” of the memory barrier protocol. In various embodiments, the opt-out decision may be made dynamically by each slave device asserting a signal, may be set system-wide during a Power-On Self Test (POST) by polling the slave devices and setting corresponding bits in a global observability register, or it may be hardwired by system designers so that only slave devices capable of performing out-of-order data transfer operations participate in the memory barrier protocol.