Abstract: A method for line-based video rate control is provided. The line based video rate control method includes system feedback to change system operating parameters, including on a packet-by-packet basis and also on a line-by-line basis. Also provided is a method for line-based compression. The method includes basic elements of an arithmetic coder to improve Golomb coding performance. By inverting operations in the method for line-based compression, the corresponding decoder can be obtained. The method also provides a heuristic-driven method for generating prediction residuals from quantized data, wherein prediction is driven in the direction of maximum correlation so that it is unnecessary to supply the decoder with additional data specifying this direction at each array element.

Abstract: A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal.

Abstract: Techniques to mitigate inter-cell interference using joint time and frequency division are described. A frequency band is divided into multiple non-overlapping frequency subbands. The transmission timeline is divided into Tin and Tout time intervals. Data is exchanged with users in at least one inner region of a cell on the entire frequency band in the Tin time intervals. Data is exchanged with users in multiple outer regions of the cell on the multiple frequency subbands in the Tout time intervals. The frequency band may be partitioned into three frequency subbands. Data may then be exchanged with users in first, second and third outer regions on first, second and third frequency subbands, respectively. The regions in which the users are located may be determined based on pilot and/or other measurements.

Abstract: A multi-band handheld communications device includes a transceiver including a transmitter having a transmit filter and a receiver having a receive filter, each of the transmit and receive filters having a bandpass region tunable across multiple bands, and a processor configured to select one of the multiple bands to operate the handheld communications device, and tune each of the transmit and receive filters based on the selected one of the multiple bands.

Abstract: The present invention provides a method and apparatus for detecting interference in a wireless communications system. The invention compares the receiver FFT output of a received signal against known sequences such as the packet synchronization sequence, frame synchronization sequence, and channel estimation sequence. By comparing the reference signal to the known sequences, the invention estimates the instantaneous signal to noise ratio (SNR) for each tone of a wireless transmission. To improve the SNR estimate, the invention computes a weighted average across multiple OFDM symbols. The invention looks for significant increases (spikes) in the SNR as a way of distinguishing interfering signals from noise. The invention can store separate SNR estimates for each transmitter in a wireless network. One embodiment of the invention uses Viterbi branch metrics in conjunction with the estimated SNR to determine the presence of an interfering signal.

Abstract: A resizable cache memory and a system including a Built-In Self Test (BIST) circuit configured to test a cache memory are disclosed. The system further includes a non-volatile storage device including an E-fuse array to store one or more indicators. Each indicator identifies a corresponding memory address of a failed location of the cache memory that has been detected by the BIST circuit.

Abstract: A memory system, and process for refreshing the memory, is disclosed. The memory system includes memory, a temperature sensor configured to measure the temperature of the memory, and a memory controller configured to refresh the memory at a refresh rate, the refresh rate being controlled as a function of the temperature measured by the temperature sensor.

Abstract: An apparatus includes a processing system configured to establish a link with any one of a plurality of access points in a mesh network, each of the access points providing the apparatus with a different data path through the mesh network. The processing system is further configured to compute a metric for each of the data paths and select one of the access points to establish the link with based on the metrics. In a centralized mesh network, an apparatus includes a processing system configured to compute, for each of the access points, a metric for each of a plurality of data paths supportable by that access point, and establish interconnections between the access points based on the metrics.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.

Abstract: Apparatus, and an associated method, for facilitating communications is a packet radio communication system, such as an IEEE 802.15.3a-compliant communication system. A deterministic sequence is used as a channel estimation sequence. The channel estimation sequence exhibits a peak-to-average ratio of lower than 8.86 dB.

Abstract: A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.

Abstract: A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and configured to control each of the word lines. The memory also includes multiplexers coupled to each of the interface ports. The multiplexers are configured to cause the selection of one of the sub-arrays based upon an address of a memory cell received at one or more of the interface ports.

Abstract: A method, system, and computer-readable medium for detecting an interferer in a wireless communication system are provided. The method includes receiving a signal having P tones, each of the P tones being associated with a frequency, determining a first signal quality of each of the P tones, determining a second signal quality of each of the P tones, and detecting the interferer that occupies the same frequency as one of the P tones based on the respective first signal quality and the respective second signal quality. The first signal quality and second signal quality behave differently when the interferer is present. The detecting the interferer includes determining a discrepancy in the behavior of the first signal quality and the second signal quality.

Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract: An Enhanced Reverse Link Encapsulation packet for a MDDI system combines and improves upon the functionality of the Round Trip Delay Measurement packet and Reverse Encapsulation packet. The combination of these packets allows for reduced MDDI link overhead when providing client reverse link transmission. This packet allows for dynamic reverse link bandwidth allocation and therefore improved MDDI link utilization.

Abstract: A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed.

Abstract: Techniques to more efficiently control the transmit power for a data transmission that uses a number of formats (e.g., rates, transport formats). Different formats for a given data channel (e.g., transport channel) may require different target SNIRs to achieved a particular BLER. In one aspect, individual target BLER may be specified for each format of each data channel. In another aspect, various power control schemes are provided to achieve different target SNIRs for different formats. In a first power control scheme, multiple individual outer loops are maintained for multiple formats. For each format, its associated outer loop attempts to set the target SNIR such that the target BLER specified for that format is achieved. In a second power control scheme, multiple individual outer loops are maintained and the base station further applies different adjustments to the transmit power levels for different formats.

Abstract: Systems and methods are described that facilitate controlling transmission/reception time slots in a wireless multi-hop ad hoc network. A node, such as an access terminal or an access point, may select an identifier that corresponds to specific time slots during which nodes with that particular identifier may transmit and/or receive. Nodes that are one hop away from each other may select different identifiers in order to ensure that neighboring nodes do not transmit and/or receive during the same time slots. In this manner, interference caused and/or experienced by a given node may be reduced.

Abstract: A low voltage differential signaling driver is disclosed and may include a current steering output circuit having a first driver output and a second driver output. The low voltage differential signaling driver may also include a programmable on-chip resistor.

Abstract: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.