Abstract: A circuit (100) for accurately tuning the absolute values of multiple parameters in a VLSI circuit by reusing a single external resistor. In the illustrative embodiment, the invention includes a first circuit (10) for generating an accurate transconductance using a single external resistor; a second circuit (20) for generating an accurate current reference using the same external resistor; and a switching circuit (60) for alternately switching on and off the first and second circuits in order to share the external resistor. The switching circuit (60) includes several switches controlled by a digital counter for turning off portions of the circuit which are not in use. In the illustrative embodiment, the invention further includes a third circuit (40) for generating one or more additional accurate reference signals. The third circuit can generate an accurate internal resistance Rint, an accurate drain to source resistance of a transistor rDS, and/or an accurate internal capacitance Cint.

Abstract: A test connector for the direct connection of electronic devices. The test connector may be mechanically and electrically connected to a testing device for insertion into a test port of an electronic device. The leading edge and the outer surface of the tip of the connector form a beveled shoulder so that insertion of the connector into a test port, misalignment of the wireless communication device with the test connector will not prevent proper insertion of the test connector into the test port. In addition, a wire encircles helically the outer surface of the tip of the test connector and functions as both a spring mechanism during the insertion of the test connector into the test port and as a grounding mechanism.

Abstract: A need to store data between a producing stage and a consuming stage commonly arises in digital processing applications. However, factors such as fabrication process limitations and circuit area constraints may restrict the amount of available storage. A novel method and apparatus for data buffering are disclosed which use less data storage than would be required by double buffering techniques.

Abstract: A system for efficiently employing a quick paging channel signal to determine the presence of a forthcoming primary paging channel in a wireless communications system employing a quick paging channel and a primary paging channel. The system includes a first mechanism for selectively processing a first quick paging channel symbol and/or a second quick paging channel symbol of a received signal based on a first decision parameter and/or a second decision parameter and providing a first indication in response thereto. A second mechanism processes the first quick paging channel symbol in response to the first indication and provides a second indication in response thereto indicating whether a forthcoming primary paging channel signal should be received and processed.