Abstract: A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.

Abstract: Semaphore operation manages exclusive access to a memory that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller is changed from a reservation state to a non-reservation state in response to receipt of the command signal.

Abstract: A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution.

Abstract: In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.

Abstract: In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.

Abstract: A bus arbitration algorithm precisely controls the relative bus channel bandwidth allocated to each master device by considering the direction of, and/or the bus channel bandwidth consumed by, a bus transaction. At least one weighting register is associated with each master device; in one embodiment, one weighting register per bus channel. The register is periodically loaded with a proportionate share of the available bus bandwidth. Upon being granted a bus transaction on a bus channel, the corresponding weighting register is decremented by an amount that reflects the bus channel bandwidth consumed by the transaction, measured in amount of data transferred or number of bus data transfer cycles required to complete the transaction. In the case of equal initial allocation of relative bandwidth share, master devices that consume bus channel bandwidth will have relatively low priority; master devices that do not consume bus channel bandwidth retain relatively high priority.

Abstract: A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.

Abstract: A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.

Abstract: A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic configured to modify the size attribute of an existing entry in the translation lookaside buffer if a new page is contiguous with an existing page referenced by the existing entry. The existing entry after having had its size attribute modified references a consolidated page comprising the existing page and the new page.

Abstract: An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary position. In one or more embodiments, the cache controller duplicates instruction data for the post-boundary position in the supplemental memory, and multiplexes that copied data into cache data obtained from the pre-boundary position.

Abstract: A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.

Abstract: A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.

Abstract: A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.

Abstract: Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.

Abstract: A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of physical registers than addressable by direct use of the IRN. The renaming register file uses a content addressable memory (CAM) to provide the mapping function. The renaming register file CAM further uses current processor state information to selectively enable tag comparators to minimize power in accessing registers. When a tag comparator is not enabled it remains in a low power state. A processor using a renaming register file with low power features is also described.

Abstract: A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to latch a first address for the first operation and a second address for the second operation. Control circuitry generates first control signals that initiate the first operation. The time duration of the first operation depends upon a delay through a delay circuit. A precharge period follows termination of the first operation. The time duration of the precharge period depends upon a propagation delay through the control circuit. The memory access of the second operation is initiated following termination of the precharging. The time duration of the second memory access depends on a delay through the delay circuit. The time when the second operation is initiated is independent of the duty cycle of CLK.

Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2?b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

Abstract: A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the requests. Slaves interconnected with the bus controller receive the requests for data and provide the requested data to the requesting masters. Control signals issued by the bus controller indicate to each slave which masters are not ready to receive the data it requested from that slave. The slaves delay transferring data to any masters that are not ready for the requested data, and provide data to different masters that are ready to receive the data they requested from the slaves.

Abstract: Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

Abstract: A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.