Abstract: A commercial instruction processor executes a decimal divide instruction by counting the number of subtractions by the divisor resulting in a positive remainder to develop the quotient. Apparatus compares the most significant decimal digit of the divisor with the most significant decimal digit of the remainder after each subtraction pass to predict if the next subtraction pass would result in a negative remainder. If so, a quotient decimal digit is stored in a memory, the divisor is shifted one decimal digit position to the right, and a series of subtraction passes are made to develop the next quotient decimal digit.

Abstract: A logic system is provided in a video system for accommodating the display of video data characters and the application of visual attributes to such characters whether occurring singularly or in fields.

Abstract: An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication busses in a data processing system, wherein the plural communication busses are electrically interconnected by ISL unit twins, and information may be transferred between plural communication busses asynchronously.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character.

Abstract: An article of furniture used to support a computer terminal or a similar object having means to continuously adjust in a stepless fashion the table top height through the operation of a single operating lever located just beneath the table top which can be operated from a seated or standing position. Swinging the operating lever in one direction in the horizontal plane releases an adjustable length gas spring controlling table top height, allowing for the raising or lowering of the table top which is followed by the return of the operating lever to its original position which locks gas spring at its new length and rigidly locks the table top at its adjusted height.

Abstract: A communication multiplexer stores the receive and transmit channel numbers of input/output devices coupled to the multiplexer by communication lines in a first-in-first out (FIFO) memory. The input/output devices are polled by sending the channel numbers from the FIFO to the input/output devices. An input/output device requesting service responds to its channel number. The remaining channel numbers in the FIFO are recirculated to give the receive channel numbers priority over the transmit channel numbers. This gives high priority to a most recently used receive channel operative in a burst mode and equal priority to all transmit channels.

Abstract: A data processing system includes a communications subsystem communicating with a number of devices. A counter monitors the communication line to detect when a communication line goes idle, that is at least 15 successive binary ONE bits appear on the line for the bit oriented protocol mode. The counter advances on successive binary ONE bits and is forced to a hexadecimal ZERO in response to a binary ZERO. If the counter reaches a count of hexadecimal F (decimal 15) a carry signal from the counter prevents the counter from advancing and initiates an idle link state.

Abstract: A cache memory for use in a data processing system wherein data words are identified by either an odd or an even address number and wherein system elements request the transfer of data words with the cache memory by supplying either an odd or an even memory request address number with a memory request, the cache memory including a first pllurality of addressable memory locations for storing data words associated with odd address numbers and a second plurality of memory locations for storing data words associated with even address numbers, and an adder for incrementing a memory request address number by one to generate the address number of the next successively stored data word to permit a set of memory address drivers to control the addressing and transferring of a data word stored in the first memory module and associated with an odd address number simultaneously with the addressing and transferring of a data word stored in the second memory module and addressed by an even address number.

Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations.

Abstract: A refresh memory address generation apparatus for a video display controller is disclosed wherein rows of character information stored in a display refresh memory may be relocated without requiring the reconstruction of the display information as stored in the display refresh memory. A roll register and PROMs precoded to perform modular addition and multiplication are used to generate an address used to access the display controller refresh memory such that all but one stationary row of information on the display screen may be scrolled (rolled) up. The scrolling of the information on the display screen is accomplished without requiring movement of the display information in the refresh memory, and the only rewrite of information in the refresh memory is done to blank the one row of information which is vacated.

Abstract: A strobe generator in a data entry input device is responsive to an input strobe signal from a keyboard system to generate a strobe signal which is not affected by electrical noise produced by electrostatically or electromagnetically induced signals in the signal lines running between the keyboard system and the data entry device input logic. An accurate output strobe signal is generated by utilizing a retriggerable logic circuit to filter out noise signals of a duration shorter than a predetermined period. The predetermined period is chosen to be less than the minimum duration of a valid input strobe signal and greater than the duration of active noise signals. The strobe generator retains the output strobe signal in the active state by use of a flip-flop until the strobe generator receives a reset signal acknowledging that the output strobe signal has been sampled by the data entry device input logic.

Abstract: In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request.

Abstract: A data processing system includes a cache store to provide an interface with a main storage unit for a central processing unit. The central processing unit includes a microprogram control unit in addition to control circuits for establishing the sequencing of the processing unit during the execution of program instructions. Both the microprogram control unit and control circuits include means for generating pre-read commands to the cache store in conjunction with normal processing operations during the processing of certain types of instructions. In response to pre-read commands, the cache store, during predetermined points of the processing of each such instruction, fetches information which is required by such instruction at a later point in the processing thereof.

Abstract: A memory controller couples to a number of memory modules and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command from a requesting device. This command when decoded causes the controller to read out from the memory modules a predetermined number of words starting with any word boundary at the location specified by the stored address portion.

Abstract: A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein an ISL unit may be reconfigured to reallocate communication bus resources without incurring excessive software overhead time losses.

Abstract: A tilt base assembly includes a base and pairs of elongated feet which attach to the bottom of a cathode ray tube (CRT) display terminal unit. The base includes a pair of trapezoidal shaped base members which attach to the ends of a horizontal plate. The elongated feet suspended from the bottom of the terminal unit rest on both inclined surfaces of each of the trapezoidal shaped base members. The front inclined surfaces of the trapezoidal shaped base members are constructed to include a plurality of indentations which provide a corresponding number of stationary positions for providing different operator viewing angles over a wide range of adjustment. Both front and rear inclined surfaces of the trapezoidal base members are provided with side walls so as to confine the terminal feet movement to the track-like areas within the side walls.

Abstract: Refresh and initialize counter circuits included within a dynamic memory system are supplemented with additional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with modulus one less than a maximum count so as to generate a sequence of counts over a corresponding number of cycles of operation for selection of row and column addresses which enable the information stored in each location of the memory system to be read out, corrected for single bit errors and rewritten back thereby rendering the system less susceptible to soft errors such as those produced by alpha particles.

Abstract: A mosaic printing head for use in a computer printer includes a needle guiding assembly and an electromagnet assembly for activating the needles. The printer head utilizes a unique design to provide for simple and fast adjustment of the position of each printing needle while eliminating any effect on the adjustment because of vibrations occurring during the printing. This design allows the needle stroke to be adjusted so as to achieve very high speed printing operation.

Abstract: A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.

Abstract: A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command or memory request from a requesting device. This command when decoded causes the controller to read out from the memory module units a predetermined number of word pairs starting with the location specified by the stored address portion.