Patents Represented by Attorney Osha & May L.L.P.
  • Patent number: 6774964
    Abstract: In a reflection type display apparatus in which a forward lightening apparatus is arranged in front of a reflection type display panel, lowering of contrast occurred when the forward lightening apparatus is turned ON is prevented. In this reflection type display apparatus, the forward lightening apparatus is adhered via an adhesive layer to a front surface of the reflection type display panel having a reflection plane. The reflection plane is constituted by a large number of first very fine patterns having a spherical shape, and a large number of second very fine patterns whose front surfaces are inclined. External light which is vertically entered into the front surfaces is reflected by the first patterns, and thereafter, the reflected external light is projected as a display along a forward direction. The forward lightening apparatus is arranged by providing a light source on a side surface of a light conducting plate having a wedge shape.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: August 10, 2004
    Assignee: Omron Corporation
    Inventors: Akihiro Funamoto, Motohiko Matsushita, Masayuki Shinohara, Masaaki Ikeda, Shigeru Aoyama
  • Patent number: 6774329
    Abstract: A switch unit is provided which is free from causing contact damage even in case applied to a high power voltage, whose switch unit is not greatly increased in size. Switches A and B are to take a motor stop status, a motor forward rotation status and a motor reverse rotation status. A switch C is to electrically connecting and disconnecting between the switches A and B and the power source. This switch C, when the switches A and B transits from the motor forward rotation status or motor reverse rotation status into the motor stop status, is operated from a connection state to a disconnection state at a time of any of completing the transition to the motor stop status and prior to a predetermined marginal period of time.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: August 10, 2004
    Assignee: Omron Corporation
    Inventors: Keiichi Shimizu, Yasuhide Tanaka, Tetsuhiko Miyoshi
  • Patent number: 6775810
    Abstract: A method for dynamically customizing object code for simulation includes obtaining a statically generated object (SGO) and a first test vector, segmenting the SGO with a marker node to generate a segmented SGO comprising a plurality of SGO segments, generating a first simulation profile using the segmented SGO and the first test vector, locating a first unexercised segment of the plurality of SGO segments using the first simulation profile, and generating a first reduced SGO by removing the first unexercised segment from the segmented SGO.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Victor A. Chang, William K. Lam, Deepankar Bairagi, Mohamed Soufi
  • Patent number: 6772299
    Abstract: A method of managing data in a cache memory includes mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines, locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache region, remapping the member of the plurality of memory addresses from the first member of the plurality of cache lines onto a second member of the plurality of cache lines within the unlocked cache region, requesting data stored in the main memory, fetching the data from the locked cache region, if available in the locked cache region, fetching the data from the unlocked cache region, if not available in the locked cache region and available in the unlocked cache region, and fetching the data from the main memory, if not available in the locked cache region and not available in the unlocked cache region.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: August 3, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas M. McWilliams, Earl T. Cohen
  • Patent number: 6771357
    Abstract: The false note detecting device 1 has a case 2 in which there are provided an ultraviolet irradiating LED 3, a light receiving element 5, an on-off switch 9, and a signal processing circuit 6 for determining an ultraviolet pattern of a note to be inspected based on an output of the light receiving element 5 to judge whether the note is true or false. By scanning the surface of the note to be inspected in hand operation, it is possible to judge the note's truth or false easily.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: August 3, 2004
    Assignee: SEL, Inc.
    Inventor: Yoshihisa Inukai
  • Patent number: 6769048
    Abstract: A cache synchronization method and apparatus for a distributed application having a client side, a server side, and an object located on either the client side or the server side are disclosed. The cache synchronization method may include detecting initiation of a transition to a new state on the client side, locating data on the client side that is to be synchronized, synchronizing located data using a cache synchronizer interposed between the client side and the server side, and completing the transition to the new state on the client side. The cache synchronizer may include a client side application usage specification (AUS) manager and a server side AUS manager. The cache synchronization method may also include synchronizing data in the object by passing to a database changes made locally to the object and allowing the distributed application to transition to a new state when synchronization is complete.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: July 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Robert N. Goldberg, Yury Kamen, Bruce K. Daniels, Peter A. Yared, Syed M. Ali
  • Patent number: 6769082
    Abstract: To enhance the accuracy of the delay time of the delay device by reducing the change in the power supply voltage for the delay device, and a delay device that delays an incoming transmission signal, comprising: a delay element that operates on a power supply voltage Vdd and a power supply voltage Vss and delays the transmission signal, the voltage Vdd being larger than the voltage Vss; an addition circuit that outputs to an output of the delay element, a predetermined voltage that is larger than the voltage Vss and smaller than the voltage Vdd. This delay element includes a digital circuit that outputs one of output voltages of two possible values in correspondence with an input voltage. Furthermore, the addition circuit outputs a voltage substantially similar to a threshold voltage that said output of the digital circuit inverts from one of the output voltages of two possible values to another thereof.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: July 27, 2004
    Assignee: Advantest Corporation
    Inventors: Toshiyuki Okayasu, Masakatsu Suda
  • Patent number: 6767631
    Abstract: The present invention aims to provide an adhesive composition showing high adhesion and cohesion as well as good heat resistance. Adhesive compositions of the present invention include an imide (meth)acrylate, a monomer having a glass transition temperature of −50° C. or less when it is homopolymerized, and a photoinitiator, wherein the content of the imide (meth)acrylate is 1-20 parts by weight per 100 parts by weight of the monomer.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: July 27, 2004
    Assignee: Sony Chemicals Corp.
    Inventors: Manabu Ono, Toshifumi Kobayashi
  • Patent number: 6768405
    Abstract: A switching device of low power consumption type, in which magnetic pole portions 37c of a pair of iron cores 37 constructing an electromagnet block 30 are individually arranged on the bottom face of a sealing case 41. The other end portions of the paired iron cores 37 are connected to each other by a yoke 39. As the electromagnet block 30 is magnetized and demagnetized, the two end portions of a moving iron member 63 of a contact mechanism block 50 are attracted by and leave the paired magnetic pole portions 37c of the iron cores 37.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: July 27, 2004
    Assignee: Omron Corporation
    Inventors: Takeshi Nishida, Yasuyuki Masui, Kozo Maenishi
  • Patent number: 6768988
    Abstract: Several types of roles are disclosed herein. The difference between the role types relates to their capabilities, which in turn derive from how they are implemented. When a client application whishes to identify all entries with some characteristic, e.g., everyone who is a manager and works in a designated building, a filtered role, which uses an LDAP filter in order to search a designated portion of the directory system and to identify those entries that possess the characteristics described in filter, is used.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: July 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: David Boreham, Peter Rowley, Mark C. Smith
  • Patent number: 6768955
    Abstract: An adjustment and calibration system for post-fabrication treatment of a phase locked loop charge pump is provided. The adjustment and calibration system includes at least one adjustment circuit, to which a phase locked loop charge pump output is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: July 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Brian W. Amick, Dean Liu, Pradeep Trivedi
  • Patent number: 6768954
    Abstract: A jitter quantity calculator comprising a timing generator, a section for calculating the value of an output signal based on a timing generated by the timing generator, first and second decision sections for deciding, respectively, whether the value of an output signal from the calculating section is equal to or greater than first and second reference values, and a section for calculating the quantity of jitter of the output signal based on the decision results from the first and second decision sections, wherein the section for calculating the quantity of jitter comprises a plurality of means for calculating the quantity of jitter, and a section for selecting any one of the plurality of means and for calculating the quantity of jitter of the output signal.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: July 27, 2004
    Assignee: Advantest Corporation
    Inventor: Hirokatsu Niijima
  • Patent number: 6763606
    Abstract: An apparatus for applying ionized particles is disclosed. The apparatus includes an ionized particle emitter for emitting ionized particles against an object; and an electric potential maintainer for maintaining electric potential of the object at a predetermined level such that the ionized particles emitted against the object by the ionized particle emitter are continuously attracted to the object while the electric potential is maintained. A method for applying ionized particles is also disclosed. The method includes emitting ionized particles against an object, and maintaining electric potential of the object at a predetermined level such that the ionized particles are continuously attracted to the object.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: July 20, 2004
    Assignee: Matsushita Electric Works, Ltd.
    Inventor: Itaru Saida
  • Patent number: 6766005
    Abstract: In one embodiment, a telephone system that includes a number of payphones intended for communication with servers via at least one communication network is disclosed. In one embodiment, the communication network includes a communication interface able to monitor communications between the said payphones and at least a first group of servers.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: July 20, 2004
    Assignee: Schlumberger Systems
    Inventor: Rodolphe Grunenwald
  • Patent number: 6762505
    Abstract: A 150 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 150 degree bump placement structures is provided.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: July 13, 2004
    Assignee: Sun Microsystems
    Inventors: Sudhakar Bobba, Tyler Thorp, Dean Liu, Pradeep Trivedi
  • Patent number: 6762981
    Abstract: A disk apparatus 10 includes a DSP 36. The DSP 36 controls each circuit component under the instruction from an MCU 44. When a braking pulse is applied to a driver 38b at the end of a jump, a corresponding tracking actuator control voltage is supplied to a tracking actuator 16. Then a DSP core 36a determines whether the TE signal level becomes equal to or below the predetermined value within a predetermined period shorter than the zero crossing cycle of the TE signal. In case the TE signal level does not become equal to or below the predetermined value within the predetermined period, the DSP core 36a determines that the travel direction of an objective lens 14 with respect to a disk 22 is reversed and applies a correction pulse having a polarity opposite to that of the braking pulse thus accelerating the objective lens 14.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: July 13, 2004
    Assignee: Funai Electric Co., Ltd.
    Inventor: Takayuki Ono
  • Patent number: 6763503
    Abstract: A method for creating a wire load model using specific interconnect configuration information is provided. Further, a program that creates a wire load model by curve-interconnect fitting parasitic information and interconnect configuration information is provided. Further, a computer system capable of creating an accurate wire load model using parasitic information specific to particular metal layers is provided.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: July 13, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Xiao-Dong Yang, Devendra Vidhani, Georgios Konstadinidis
  • Patent number: 6759877
    Abstract: A method and apparatus that dynamically control an amount of offset current generated by a keeper device are provided. Further, a method and apparatus that use a temperature-controlled keeper device to dynamically optimize an evaluation performance of a dynamic circuit are provided. In particular, when IC temperature is relatively high, i.e., there is increased current leakage in the dynamic circuit, an amount of offset current output by the temperature-controlled keeper may be increased, thereby preventing a dynamic node of the dynamic circuit from being discharged, or otherwise adversely affected, by the increased current leakage. Alternatively, when the IC temperature is relatively low, i.e., there is decreased current leakage in the dynamic circuit, the amount of offset current output by the temperature-controlled keeper may be decreased, thereby ensuring that the offset current is not so large that it severely degrades the evaluation performance.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: July 6, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Shaishav A. Desai, Claude R. Gauthier, Anup S. Mehta
  • Patent number: 6759182
    Abstract: There is provided a manufacturing method of an optical device having a micro-asperity pattern that has various kinds of accurate three-dimensional shapes and is realized as thin films. A substrate is coated with a resin thin film made of a photosensitive resin, and the temperature of the resin thin film is controlled so as to be lower than the photosensitivity extinction temperature of the resin thin film. A micro-asperity pattern of a stamper is pressed against the resin thin film when the resin thin film is in a softened or melted state by pressurizing means, whereby a micro-asperity pattern is formed on the surface of the resin thin film.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: July 6, 2004
    Assignee: Omron Corporation
    Inventors: Masaaki Ikeda, Akihiro Funamoto, Motohiko Matsushita, Shigeru Aoyama
  • Patent number: D494318
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Tsuyoshi Nishizawa, Toshiaki Nakajyo