Abstract: A base plate for a suspension assembly in a hard disk drive wherein the base plate has a hardened flange and soft hub. The base plate is stamped in a progressive die in a sequence of forging and coining operations. The base plate is subsequently fully annealed to allow the material to yield at a low stress level so that the hub will create a press fit against the inner wall of an actuator arm boss hole. The base plate is passed through a secondary coining operation following the annealing step to work-harden the flange portion only. The result is a base plate with a flange portion that is hardened and a hub portion that is softer than the flange portion. The advantage is that the hardened flange is more resistant to deformation of a load beam welded thereto and the hub is more disposed to plastically deform and harden during swaging which is desirable for maintaining a press fit.

Abstract: A compact expansion card to replace an Extended Industry Standard Architecture (EISA) card. An EISA card has an edge connector of 188 pins of a given width and a given gap between pins, in 5.5 inches, two rows on a front of the EISA card and two rows on a back of the EISA card. The 188 pins include 157 signal pins, 10 pins dedicated to a +5 volt supply, and 18 pins dedicated to ground. The compact expansion card has an edge connector of 162 pins in 4.5 inches in two rows, one row of 81 pins on a front of the compact card and one row of 81 pins on a back of the compact card, a gap between each of the 162 pins being the same as the given gap between pins of the EISA card. The 162 pins include 157 signal pins, one +5 volt pin dedicated to a +5 volt supply, and one ground pin dedicated to ground. The 157 signal pins are of the same given width as the 157 signal pins of the EISA card.

Abstract: A computer having a motherboard housed in a chassis having a bottom panel and a rear panel perpendicular to the bottom panel. The rear panel has a cutout therein. The motherboard is secured to the chassis in parallel with the bottom panel. The motherboard has a socket and the audio card is mounted in the socket perpendicular to the motherboard. The audio card has connectors, such as audio line-in, line-out, microphone, speaker power and game port, mounted perpendicular to the audio card such that the connectors are aligned with the cutout in the rear panel. The audio card is grounded to the chassis with an electromagnetic interference (EMI) gasket contoured to the cutout.

Abstract: A 25-pin cable socket has serial pins and parallel pins. Pins 18 through 25 are at ground level only if a parallel cable is inserted in the socket. Serial communication lines are provided to a serial controller and parallel communication lines are provided to a parallel controller. A OR is connected to the pins 18 through 25. A switch is connected to the output of the OR. If ground is sensed at the pins 18 through 25, the OR output is asserted causing the switch to be activated to connect the parallel pins associated with parallel operation to the parallel communication lines. If ground is not sensed at the pins 18 through 25 the switch is deactivated to connect the serial pins associated with serial operation to the serial communication lines.

Abstract: A parallel processor network comprised of a plurality of nodes, each node including a processor containing a number of I/O ports, and a local memory. A communication path is established through a node by comparing a target node address in a first address packet with a processor ID of the node. If node address is equal to the target node address a receive channel is allocated to the input port and a route ready command is sent over an output port paired with the input port. If the node address is not equal to the target node address, then a first unallocated output port is selected from a port vector and the address packet is forwarded to a next node over the selected output port.

Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt-to-3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5 V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip. VSS ground on board pins are connected in common to both the ground terminal of the voltage regulator and the VSS pads of the chip.

Abstract: A computer includes a mother board having a clock A thereon that provides a primary clock to a clock distribution buffer that distributes the clock that drives it to clock electronic components on the mother board. The mother board has a socket for receiving an optional module having a clock B thereon. A clock switching circuit is connected to the clock A and to the clock B socket terminus. An edge detector connected to clock B detects an edge of the clock B. A detection window indicator is asserted upon a predetermined condition, such as that power is on and stable. A control circuit, connected to the clock switching circuit, to the edge detector and to the detection window indicator causes the secondary clock to be selected and substituted for the primary clock.

Abstract: A manifold expansion card connector on the motherboard of a personal computer. The computer connector comprises a base, there being a number of pins in the base. An upper portion has three sockets, each socket having connectors therein that are connected to the pins. A first socket is oriented in a plane horizontal to the plane of the pins. A second socket is oriented in a plane vertical to the plane of the pins. A third socket is oriented in a plane at an angle, such as 45 degrees, to the plane of the pins. Two of the connectors placed side by side provide for six add-in cards in a computer that has two different buses, such as a PCI bus and an ISA bus. In a computer with a single bus, such as a PCI bus or an ISA bus, a single manifold expansion card connector provides for seven cards with a single multi-pin connector to the bus.

Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt- to- 3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip.

Abstract: A computer mother board is housed in a chassis that has a number of expansion board guides along a back panel of the chassis and a power supply with a cooling fan. The mother board is rectangular with its short dimension being 8 inches and its long dimension being as 13 inches so that it fits into the chassis of existing computers. The motherboard is positioned in the chassis such that the long dimension is along the back panel of the chassis, which means that the motherboard is rotated 90 degrees from the orientation of conventional motherboards. The short dimension accommodates a number of expansion card connector sockets perpendicular to the long dimension such that the connector sockets are in alignment with the expansion board guides along the back panel of the chassis. A central processing unit socket is located near the power supply fan for more efficient cooling.

Abstract: A cache controller tag random access memory (RAM) is configured into two ways, each way including tag and valid-bit storage for associatively searching a directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. There are two lines selected during a line fill to one of the ways. A least recently used (LRU) pointer selects which way to fill on a line fill cycle. The right way is selected for a line fill in response to right hit signal provided that the LRU pointer points to the right way. The LRU pointer is flipped to point to the left way upon the filling of the right line of the right way. The left way is selected for a line fill in response to a left hit signal provided that the LRU pointer points to the left way. The LRU pointer is flipped to point to the right way upon the filling of the left line of the left way.

Abstract: A computer having a motherboard moused in a chassis having a bottom panel and a rear panel perpendicular to the bottom panel. The rear panel has a cutout therein. The motherboard is secured to the chassis in parallel with the bottom panel. The motherboard has a socket, such as a single in-line memory module (SIMM) socket. The I/O riser card is mounted in the socket perpendicular to the motherboard. An I/O riser card has connectors such as Standard 9 pin D-Sub, 25 pin D-Sub, Keyboard/Mouse Mini DIN, SCSI 2, wide SCSI and Pin Connectors mounted on the I/O riser. The connectors are mounted perpendicular to the I/O riser card such that the connectors are aligned with the cutout in the rear panel. The connectors are grounded to the chassis with an electromagnetic interference (EMI) gasket contoured to the cutout.

Abstract: An in-circuit emulator trace bus clocking mechanism. A synchronization clock associated with the trace bus is provided. Arrival of a first event on a microprocessor bus to be traced is signified by a transition of a control line. A start of cycle event is detected. A start of cycle signal is generated with respect to the start of cycle event. A two stage pipeline having stage 1 storage elements and stage 2 storage elements are connected to receive data from the microprocessor bus. The start of cycle signal is used to sample data from the microprocessor bus into the stage 1 storage elements. An end of cycle event is detected. An end of cycle signal is generated with reference to the end of cycle event. The end of cycle signal is used to sample data from the stage 1 storage elements into the stage 2 storage elements. The end of cycle signal is also used to sample data appearing on the microprocessor bus at the end of the cycle into the stage 2 storage elements.

Abstract: A data processing system comprised of a memory, a translation lookaside buffer (TLB) providing access to the memory, and an instruction cache connected to the memory. A two entry translation write buffer (TWB) has a first entry that is a first logical register and an associated first physical address register and a second entry that is a second logical register and an associated second physical address register. A physical address bus is connected to the TWB and a logical address bus is connected to the TLB and to the TWB, the logical address bus presenting an instruction pointer to the TLB and to the TWB. The instruction pointer is comprised of logical address bits including upper order bits, lower order bits, and a single bit having a first value or a second value. The single bit provides for translation of even-number pages for which the single bit has the first value and for odd-number pages for which the single bit has the second value.

Abstract: A micro processor emulator in which a set of core micro processor registers are the communication interface between an external system and a core-ported memory. The registers are connected to a serial scan port for transfer of information between a halted emulation environment and the external system. The serial port includes a command register that receives a jump address to initiate execution of a software monitor. Two special bits are provided in the command register, one that indicates a break, and one that indicates a Fast Break GO. This provides a break mechanism for a micro processor chip which does not have a dedicated memory bus. This break mechanism is the mechanism by which a halt or an asynchronous break is effected. After a fast break, the Fast Break GO mechanism does the action described by one command, and then immediately goes back to emulation without any external processor intervention.

Abstract: A dynamic clock switching circuit in which a multiplexer (MUX) is connected to clock A and clock B. MUX control lines are encoded to signal clock A or clock B. A MUX control change detector is connected to the multiplexer and to the MUX control lines. A MUX control change detector decodes the MUX control lines and asserts a MUX change signal upon a condition that a change from one clock to another is signaled. A Hold Sync flip-flop is connected to a hold output of a Hold Start flip-flop. The Hold Sync flip-flop is connected to and clocked by the clock A. A Hold Disable flip-flop is connected to an OK to change output of the Hold Sync flip-flop. The Hold Disable flip-flop is connected to and clocked by clock A. A Clock Sync flip-flop is connected to a hold disable output of the Hold Disable flip-flop. A reset input of the Hold Start flip-flop is connected to a clock sync output of the Clock Sync flip-flop. An AND is connected to the hold output and to the hold disable output.

Abstract: Apparatus for enabling internal data processing logic including a number of units clocked at a first frequency to operate with an external bus operating at a second frequency that is a fraction m/n of said first frequency. A first bus is connected via readers to data latched for data transfer from the number internal units of the data processing logic to the data latches. A second bus is connected via drivers to the data latches for data transfer from internal bus units to the data latches. The data latches are connected to the external bus. A control circuit connected to the readers and drivers controls the readers and drivers to guarantee that sampling is done when logic is stable. The control circuit includes priority logic for determining priority between the units for permitting a high priority unit to transfer data on the external bus.

Abstract: A microprocessor comprised of Instruction Fetch Unit (10), Instruction Decoder (12), Pipeline Sequencer (14), Register File (16), Multiply/Divider-Unit, Execution Unit, and REG coprocessors block (18) and instruction cache, Address Generation Unit, local register cache, and MEM coprocessors block (20). The Instruction Cache provides the Instruction fetch unit (10) with instructions every cycle. The instruction sequencer (IS) includes the Fetch Unit (IFU-10), the Instruction Decoder (ID-12) and the Pipeline Sequencer (PS-14). The instruction sequencer can decode and issue up to three instructions per clock. The pipe sequencer (14) employs a write back path to store snap shots of the state of the machine in pipe stages 1 and 2.

Abstract: Logic examines signals from an instruction fetch unit to determine if the next instruction is a branch. A mux selects one of the 4 instruction words. MACRO [0:3] and a displacement from the selected word. A full adder (40) adds this displacement to the instruction pointer. The result is used as the branch address. The timing is such that a 1 clock lookahead is sufficient to hide this calculation from program execution. The branch register address is determined by the process ID and the macro mode state bit. The branch by pass mechanism causes the branch address to be driven from the calculation instead of a branch register. If a branch fail or scoreboard hit occurs, a write cancellation is generated to stop the current address calculation from being stored in a branch register. If a branch fail or scoreboard hit does not occur, then the current address calculation is stored in a branch register. If a branch bypass occurs, then the branch address is driven from the calculation.

Abstract: An apparatus for protecting the data in a local register cache during calls and returns that cross subsystem boundaries. The left most bit of a shift register is set to a 1 if a "set boundary bit" instruction is detected. A subsequent PUSH instruction shifts the shift register right one bit. A POPTOS1 instruction in the instruction flow signifies an intra-subsystem return and causes the leftmost bit of the shift register to be checked to see if it is a zero. A protection fault is signalled upon the condition that the leftmost bit is not equal to zero. The shift register is shifted left one bit upon the condition that a POPSTOS 2 instruction is detected. A POPSUB1 instruction detected in the instruction flow signifies an inter-subsystem return and causes the leftmost bit of the shift register to be checked to see if it is a one. A a protection fault is signalled upon the condition that the leftmost bit is not equal to zero.