Abstract: A self-scanning linear array (10) is moved (12) in the image plane of a lens to thereby scan the image of an object which has been focused in the image plane. A random access controller controls random access to the information within the scanned image. Commands (14) including mechanical positional parameters (16) and electronic scan parameters (18) are decoded by the master microprocessor (20). The electronic scan parameters in the command provide information such as a user selected transverse axis frame size scan output of the array. An address generator (22) generates addresses in response to output pulses from the array. A windowing sequencer (24) in conjunction with the address generator (22) selectively gates particular ones of the pulses in the train of output pulses from the array in accordance with the electronic scan parameters in the command.

Abstract: An electronic camera in which a linear array (10), comprised of a row of light-sensitive devices, is mechanically moved in the image plane while being electronically scanned orthogonally to the direction of movement to capture the image. The array (10) is held in the image plane of a lens by a carriage (14) onto which the array is attached. One end of a flexible band (18) is connected to one end (20) of the carriage (14). The flexible band (18) is partially wrapped around a capstan (30) and a turnaround idler wheel (32). The other end of the flexible band (18) is connected to other end (24) of the carriage (14). A motor (34) drives the capstan (30) through a reduction gear to cause the flexible band (18) to move and thereby cause relative motion between the array and the lens.

Abstract: A nonclock-synchronous interface between a microprocessor and a coprocessor. A request line (404) from the coprocessor and an acknowledgment line (402) from the microprocessor provide for operand transfer from the coprocessor to the microprocessor. A busy line (410) and an error line (408) from the coprocessor allow the microprocessor to monitor the condition of the coprocessor. Data (406) are transferred through a data channel in the microprocessor using the full memory management and protection mechanism of the microprocessor so that the protection mechanism is not circumvented. A memory-read cycle is generated using the address taken from the memory-address register (401). The data is buffered inside the microprocessor and the coprocessor's request is acknowledged. The memory-address register is then incremented by a predetermined amount and an I/O write cycle is generated using a prewired address into the coprocessor.

Abstract: Data processing logic (10) is fabricated on an integrated circuit device and is outputted to a plurality of output pins (1-N). A number of these pins (34, 36, 38) which are normally function outputs, and a reset pin (24), are used to invoke a test state on the integrated circuit device. Test control logic generates two test flags (TA, TB) in response to test signals on two of these pins (34, 36). These two test flags are decoded (14, 18, 20, 22) to control all signal output pins (1-N) from the integrated circuit device by forcing a high-level, low-level, or high-impedance condition, as selected by external stimulus at the output pins, regardless of the condition of the internal circuitry on the integrated circuit device. A test flag TC (60) is generated in response to a test signal on pin (38). This TC flag is used to signal the data processing logic (10) to initiate a functional self-check operation.

Abstract: A disk drive that generates a smooth spiral during the recording of data so that the recording operation is continuous. A magnetic read/write head (2) is mounted on an arm (4) so that it can move generally along a radius of a disk (8). A rotary motor (12) is used to spin the disk and to drive a gear train. The output of the gear train is used to move the arm-mounted head across the disk. The pitch of the spiral generated is controlled by the relative gear ratio between the disk and the head mechanism. Rapid retrace of the head mechanism to its starting position is accomplished by placing a return spring (56) on the head mechanism and a clutch (42) in the gear train. The location of the clutch in the gear train is chosen so that the head mechanism, while being returned to the starting position under spring power, spins a neutral pitch fan (102). The energy dissipated by churning the air by the fan limits the peak velocity of the head mechanism.

Abstract: A disk drive having a head actuator that is capable of quick, fine adjustments in position of the transducing head in order to precisely follow data tracks. A magnetic read/write head (2) is mounted on a first arm (4) so that it can move generally along a radius of a disk (8). A rotary motor (12) is used to spin the disk. A primary motor (36) in conjunction with a cable (42) and drum (40) is used to move the arm-mounted head in coarse movements across the disk. A secondary motor (32) in conjunction with a second arm (34) is used to move the arm-mounted head in fine movements across the disk. The primary motor may be used for track jumping, while the secondary motor may be used for track following.

Abstract: A number of intelligent nodes (bus interface units-BIUs and memory control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Error-detection mechanisms deal with information flow occuring across area boundaries. Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error report lines (106, 108). If an error recurs the node at which the error exists initiates an error message which is received and repropagated on the error report lines by all nodes. The error message identifies the type of error and the node ID at which the error was detected. Confinement area isolation logic in a node isolates a faulty confinement area of which the node is a part, upon the condition that the node ID in an error report message identifies the node as a node which is a part of a faulty confinement area.

Abstract: A number of intelligent nodes (bus-interface units-BIUs and memory-control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error-report lines (106, 108). Processor modules (110) and memory modules (112) are each connected to a node which controls access to a common memory bus (107). Each node includes means (a married bit-170 and a shadow bit-172) for marrying modules in pairs such that each module in the pair tracks the operations directed to the module pair, and each module in the pair alternates with the other module in the handling of requests or replies. Each node registers the ID of the other node in a spouse ID register.

Abstract: A playback head (155) is moved across a recording medium (151) orthogonally to a data track by playback head-moving means (157, 159, and 161), said data track being independently moved so that previously-recorded data is sequentially recovered. An electrical signal, which bears a direct relationship to the velocity of the head-moving means, is produced by a position sensor affixed to the head-moving means and a differentiator (169). Said signal is used to close a velocity loop, through a summing junction (171) and a power amplifier (173), around the head-moving means. The playback head is moved in addition, at a relatively high frequency, by dithering means which causes an amount of head motion that is small with respect to the width of the data track. The dither motion causes an amplitude modulation of the signal being recovered from the data track by the playback head.

Abstract: A number of intelligent bus interface units (100) are provided in a matrix of orthogonal lines interconnecting processor modules (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits. Write-request packets and read-request packets are issued to the memory-control unit.

Abstract: A high-resolution, electronic camera with real-time storage capability. The image at the focal plane of a lens (5) is electronically scanned in one direction by a linear photodiode array (1), and in the orthogonal direction by a carriage (3), motor (17), and leadscrew (13) subassembly which mechanically moves the array with respect to the lens. The motion of the array is directly translated into comparable relative motion of a recording head (19) with respect to a recording media (21) so that scanned pixel information is recorded on the media (21) concurrently with its generation.

Abstract: An arbitration mechanism comprising a request FIFO (408) for storing ones and zeros corresponding to received requests in the order that they are made. A one indicates that the request was made by the module in which the FIFO is located, and a zero indicates that the request was made by one of a number of other similar modules. The request status information from the other modules is received over signal lines (411) connected between the modules. This logic separates multiple requests into time-ordered slots, such that all requests in a particular time slot may be serviced before any requests in the next time slot. A store (409) stores a unique logical module number. An arbiter (410) examines this logical number bit-by-bit in successive cycles and places a one in a grant queue (412) upon the condition that the bit examined in a particular cycle is a zero and signals this condition over the signal lines.

Abstract: An apparatus for the very precise centering of a flexible recording disk (2) onto a disk-drive spindle (8), for clamping it firmly for spinning, and for the easy removal thereof. Disk (2) is provided with a reinforced center hole (4) so that it can be manufactured to a tight tolerance. Spindle (8) is provided with a precision-alignment cylinder (12) over which the disk must slide in order to rest on a spindle seat (6). Once disk (2) is resting on spindle seat (6), it is clamped there by a self-aligning, rotatable spindle cap (24), which is brought down on top of the disk. The disk is centered for sliding along the alignment cylinder through the action of a conical surface on cone (14). The cone (14) in its entirety may be part of spindle (8), or alternatively, in order to facilitate insertion and removal of the disk, part of the cone may be integral to the clamping-spindle cap (24), or be a retractable plug.

Abstract: A memory management and protection mechanism in which access to protected entitites is controlled. The protected entities are represented by descriptors. Each protected entity is accessed via a selector which comprises an index integer assigned to the descriptor at the time of its creation. Tasks are active entities which may perform accesses and therefore are subject to control. A task has certain access rights. Each protected entity is assigned a specific privilege level. Each task within the system operates at one and only one privilege level at any instant in time. Protected entities which reside at a privilege level which is equal or less privileged than the current privilege level (CPL) of the task are generally accessible. The effective privilege level (EPL) of an access to a protected entity is defined as the numeric maximum of the CPL and the requested privilege level (RPL) present in the selector pointing to the memory segment to be accessed.

Abstract: A number of intelligent crossbar switches (100) are provided in a matrix of orthogonal lines interconnecting processor (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding error-reporting lines (106); and memory buses (107) with corresponding error-reporting lines (108). At the intersection of these lines is a crossbar switch node (100). The crossbar switches function to pass memory requests from a processor to a memory module attached to an MCU node and to pass any data associated with the requests. The system is organized into confinement areas at the boundaries of which are positioned error-detection mechanisms to deal with information flow occurring across area boundaries. Each crossbar switch and MCU node has means for the logging and signaling of errors to other nodes. Means are provided to reconfigure the system to reroute traffic around the confinement area at fault and for restarting system operation in a possibly degraded mode.

Abstract: An apparatus which monitors a subset of control panel inputs in a nuclear reactor power plant, the subset being those indicators of plant status which are of a critical nature during an unusual event. A display (10) is provided for displaying primary information (14) as to whether the core is covered and likely to remain covered, including information as to the status of subsystems needed to cool the core and maintain core integrity. Secondary display information (18, 20) is provided which can be viewed selectively for more detailed information when an abnormal condition occurs. The primary display information has messages (24) for prompting an operator as to which one of a number of pushbuttons (16) to press to bring up the appropriate secondary display (18, 20). The apparatus utilizes a thermal-hydraulic analysis to more accurately determine key parameters (such as water level) from other measured parameters, such as power, pressure, and flow rate.

Abstract: An instruction translator unit which receives an instruction stream from a main memory of a microprocessor, for latching data fields, for generating microinstructions necessary to emulate the function encoded in an instruction, and for transferring the data and microinstructions to a microinstruction execution unit over an output bus. The instruction unit includes an instruction decoder (ID) which interprets the fields of received instructions and generates single forced microinstructions and starting addresses of multiple-microinstruction routines. A microinstruction sequencer (MIS) accepts the forced microinstructions and the starting addresses and places on the output bus correct microinstruction sequences necessary to execute the received instruction. The microinstruction routines are stored in a read-only memory (ROM) in the MIS. The starting addresses received from the ID are used to index into and to fetch these microinstructions from the ROM.

Abstract: A medieval game combining both fantasy game elements and strategy game elements with chance. Each player assumes a role of a king (or queen) to manipulate men, gold, and circumstances (represented in playing cards) in an effort to gain possession of an opponent's crown. The game pieces include a game board with castles represented thereon for defending each player's crown, and squares thereon with indicia which enable a player to draw a card when a game piece lands on one of the indicia. The cards represent men, gold, attack and defend moves, and circumstances such as penalties and rewards. The play is advanced by utilizing a white knight game piece and a black knight game piece for each player. The game pieces advance around the board in accordance with chance, such as the throw of a die.

Abstract: A microprocessor receives addresses and data from a peripheral subsystem for use in subsequently accessing portions of the main memory of a data processing system in a controlled and protected manner. Each of the addresses is used to interrogate an associative memory to determine if the address falls within one of the subranges for a "window" on the main memory address space. If the address matches, then it is used to develop a corresponding address on the main memory address space. The data associated with the peripheral subsystem address is then passed through the interface and into the main memory at the translated memory address. Data transfer is improved by buffering blocks of data on the microprocessor. Data bytes are written into the buffer at a slower rate than data blocks are read out of the buffer and into main memory. A buffer bypass register allows single bytes of data to be transferred to a single address by bypassing the buffer.

Abstract: A communication mechanism for use in a multi-processing system wherein several processors share a common memory. Each processor has associated with it a local communication segment, stored in memory. The local communication segment is for processor-specific communication. Another segment, the global communication segment, is common to all processors, and is for system-wide communication. Each communication segment has a field containing control flags. The flags are set by one processor and later inspected by the same or another processor. The inspecting processor is instructed to perform a number of functions specified by the state of the control flags. A count field and a lock field are provided in all communication segments to interlock access to the communication mechanism. A status field is provided in the local communication segments.