Abstract: A notebook personal computer (PC) in which an I/O connector and module are located at the top of the display screen. The module is L-shaped to conform to the shape of the display screen housing with the connector to the internal printed circuit input/output (I/O) card extending into the notebook PC frame. The connector is constructed so as to mate with I/O cards which are fitted with a standard I/O card contact design.

Abstract: An interface protocol between a microprocessor register file (6) and a plurality of first functional units capable of independently executing first microinstructions that take a plurality of clock cycles to complete execution. A plurality of second functional units capable of independently executing second microinstructions that take a single clock cycle to complete execution. The first and second microinstructions are issued by an instruction decoder. A microintruction bus (112) is connected to the instruction decoder, the register file, and to each of the first and second functional units. A REG interface and a destination bus (110) are also connected to the register file (6). A Scbok line (102) is connected between the instruction unit, the register file and to each one of the first and second functional units. The instruction decoder includes means for asserting the Scbok line to signal that a current microinstruction on the microintruction bus (112) is valid.

Abstract: An instruction fetch unit in which an early instruction fetch is initiated to access a main memory simultaneously with checking a cache for the desired instruction. On a slow path to main memory is a large main translation lookaside buffer (TLB) that holds address translations. On a fast path is a smaller translation write buffer (TWB), a mini-TLB, that holds recently used address translations. A guess fetch access in initiated by presenting an address to the main memory in parallel with presenting the address to the cache. The address is compared with the contents of the TWB for a hit and with the contents of the cache for a hit. The guess access is allowed to proceed upon the condition that there is a hit in the TWB (the TWB is able to translate the logical address into a physical address) and a miss in the I-cache (the data are not available in the I-cache and hence the guess access of main memory is necessary to get the data).

Abstract: A hub in a star local area network (LAN) in which a number of slave hubs are connected to a master hub. A number of slave stations are connected to each slave hub. A SREQ link and a MACK link connect the master hub and the slave hubs. A slave local preferred station is selected at the slave hub from among ones of the slave stations that attempt to transmit a frame simultaneously. The slave transmits a slave local preferred station frame over the SREQ link. A master preferred station is selected at the master hub from among the slave local preferred station frame and ones of the plurality of master local stations that attempt to transmit a frame simultaneously. A small FIFO at each hub is provided to maintain collision resolution. Upon a condition that a master preferred station ID and a slave local preferred station ID are not identical, the slave hub flushes its small FIFO and adds the local preferred station to its local non-preferred station list.

Abstract: A micro processor emulator in which an SMM flag is set whenever a processor being emulated enters system management mode (SMM) mode, a diminished power mode, and is reset when the processor leaves SMM mode. Events, such as branch instructions, that are recorded in a trace memory while the processor is in SMM mode (when the SMM flag is set) are recorded as a trace frame comprised of a trace word and an associated in system management mode (IN.sub.-- SMM) trace bit. When a user evokes interrogation mode of the emulator, the IN.sub.-- SMM trace bit is used to calculate correct physical addresses for disassembly of the recorded trace information.

Abstract: A processor communicates over a memory bus with a main memory and a cache by asserting an address strobe signal (ADS) to initiate a memory access. The cache includes a cache controller and a tag random access memory (tag RAM). Internal cycles are tracked by a first logic in the tag RAM that responds to an external cycle (EXCYC) signal and asserts an internal cycle (INCYC) signal during a time when a request to the tag RAM is pending. A second logic combines the INCYC signal with the. ADS to generate an address strobe wait (ADSWAIT) signal. A third logic combines the ADSWAIT signal with the ADS to generate an address strobe cycle (ADSCYC) signal. A fourth logic responsive to one of several end-of-cycle signals generates a terminate signal to signify an end of a current cycle. A fifth logic asserts the EXCYC signal in response to the ADSCYC signal and unasserts the EXCYC signal in response to the terminate signal.

Abstract: An in-circuit emulator on an integrated circuit chip having an input pin for externally triggering on-chip break mechanisms. A break logic having an arm input is connected to an instruction pointer counter (IP counter). The break logic matches the IP counter to an instruction execution address. A counter is provided that once started runs a period of time and then shuts itself off, the length of the period of time being equal to the amount of time it takes for the break logic to arm after assertion of the arm input. A break logic control is connected to the input pin activates the arm input in response to signals on the input pin. The break logic control also starts the counter.

Abstract: A parallel processor network comprised of a plurality of nodes, each node including a processor containing a number of I/O ports, and a local memory. Each processor in the network is assigned a unique processor ID (202) such that the processor IDs of two processors connected to each other through port number n, vary only in the nth bit. Input message decoding means (200) and compare logic and message routing logic (204) create a message path through the processor in response to the decoding of an address message packet and remove the message path in response to the decoding of an end of transmission (EOT) Packet. Each address message packet includes a Forward bit used to send a message to a remote destination either within the network or to a foreign network. Each address packet includes Node Address bits that contain the processor ID of the destination node, it the destination node is in the local network.

Abstract: A cache controller tag ram is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. First means are provided for asserting a flush signal upon the condition that a warm start reset is recognized or a power up condition is recognized. Logic causes all pending write requests to be withdrawn in response to the flush signal. The directory is cleared by setting all valid, write protect and least recently used (LRU) bits to zero in both of the ways. Subsequent write requests use a line fill algorithm to ensure that correct data is written into the directory by choosing which way to select for a line fill after the bits have been cleared.

Abstract: A hub in a star local area network (LAN). A single station, called the preferred station, is dynamically selected to perform a transmission. When two or more stations attempt to transmit simultaneously, one currently preferred station goes through, while all others sense collisions. The currently preferred station is dynamically selected by performing a precedence algorithm which is a fairness and deterministic algorithm. If the station receiving from the preferred station also attempts to transmit, then it senses a collision and the hub lets it recover and enable itself for receiving before transmitting the frame. This is done by storing the preferred station frame in an internal small first-in first-out (FIFO) buffer. The hub resends the frame from the FIFO immediately after Inter Frame Spacing (IFS) while the receive station attempts to transmit later. If after a number of attempts the hub does not succeed in transmitting the frame successfully, then the hub generates a collision frame.

Abstract: A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encoded cache state bits. A first bus connects the microprocessor to the cache, the first bus including backside bus cache directory tags signals comprised of address bits used for a cache hit comparison in the directory RAM and backside bus cache directory state bits for determining a state encoding of a set in the directory RAM. A second bus connects the microprocessor to the main memory. The directory includes means for comparing the cache directory tags on the first bus with the tags stored in the directory and for asserting a Bmiss signal upon the condition that the directory tag stored in the backside bus cache directory do not match the backside bus cache directory tags signals.

Abstract: A cache controller sits in parallel with a microprocessor bus and includes a tag RAM for associatively searching a directory for cache data-array addresses. Two normal address latches are provided to capture a cycle address in case the current cycle is extended by a pending tag RAM access. At any time, except when the next cycle has started, but during which the current cycle is in progress, one latch is open to an input buffer such that the input address is latched by that latch. The other latch holds the current cycle address until the cycle ends. The current cycle can be extended with snoops. The current cycle address has to be maintained as long as the cycle is still in progress. In the meantime, the external cycle might have ended and a next cycle started. The second address latch is used to capture the address corresponding to this new cycle. As signal selects which of the two latches will supply the address via a MUX to the tag RAM.

Abstract: A processor in which instructions and data at logical addresses are mapped onto real memory locations at physical addresses that are translated from the logical addresses by a translation lookaside buffer (TLB) that takes one clock phase to perform this function. The TLB only needs the upper 20 bits of a logical address, which bits correspond to the logical page number, to do the translation to a physical address. The lower 12 bits are not needed until the TLB translation is done. The add of the "base-plus-displacement/offset" usually does not cross a page boundary, that is, the upper 20 bits are the same after the add. A mechanism takes this into account and guesses that the upper 20 bits will not change, and sends them to the TLB. In parallel with the TLB translation, the effective address add of the "base-plus-displacement" is computed.

Abstract: A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected.

Abstract: A programmable gate array comprised of a number of configurable functional blocks. Each configurable functional block has a number (m) of inputs. A global interconnect matrix interconnects the configurable functional blocks. The global interconnect matrix provides for routing any combination of signals entering the matrix to any configurable functional block, up to and including the maximum number (m) of inputs of a configurable functional block. Each configurable functional block includes a product term array connected to the m inputs. The product term array can perform a logical AND of up to m bits. A compare term array is also connected to the m inputs. The compare term array can perform an identity compare of up to m/2 bits. A number n of macro cells are provided in each configurable functional block wherein the number n is less that the number m.

Abstract: An integrated circuit module in which an error detection circuit compares data generated internally on module with data generated externally from another substantially identical module. An error detect output is asserted upon the condition that data generated internally on module and data generated externally from module do not match. A circuit alters the internally generated data by injecting a zero bit and then a one bit data into the internally generated data to thereby generate altered data. Error anticipation control logic generates a test condition, which corresponds to the expected error condition caused by altered data, by first expecting to detect the effect of the injected zero bit and then expecting to detect the effect of the injected one bit. An error-0 comparison circuit compares the actual error detect output with expected error detect output for the zero bit. An error-1 comparison circuit compares the actual error detect output with expected error detect output for the one bit.

Abstract: A floating point unit multiply logic in which a sticky bit is computed in parallel with partial product generation and reduction for three different rounding precisions and two different operand, ranges. Two sticky bits need to be calculated during the parallel operation because the result can be anywhere between 0 and 4 and it will not be known which is correct until after the result of the multiplication has been calculated. If the result is between 0 and 2, then a first sticky bit is generated. When the result is between 2 and 4, a second sticky bit is generated. It is not known which sticky bit is the correct one to use until the final addition is performed. Once the results of the final addition is known, the correct sticky bit is selected using a carry out from the adder, the overflow bit. If the overflow bit is a 1, then the first sticky bit is selected. If the overflow bit is a 0, then the second sticky bit is selected.

Abstract: A floating point number which includes a mantissa field, an exponent field, and a sign field is converted to an integer of n-bit size including a sign bit. The sign field is examined to determine if the floating point number is a positive or negative number. The mantissa field is shifted right to thereby denormalize the mantissa resulting in a shifted mantissa. If the floating point number is a negative number, zero is subtracted from the shifted mantissa to produce a result mantissa field that is a two's complement number. Otherwise, zero is added to the shifted mantissa to produce a result mantissa field. Overflow or underflow of the result mantissa field with respect to the integer of n-bit size is detected and the sign bit is set appropriately to reflect the fact that the sign field of the floating point number is a negative or positive number.

Abstract: A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.

Abstract: Apparatus for converting to a single precision or double precision number an extended precision floating point number comprised of a sign field, an exponent field and a mantissa field. A sticky generation logic connected to the mantissa bus calculates rounding bits for single and double precision and places the rounding information at a sticky output. Overflow and underflow detection logic connected to the exponent bus detects exponent overflow and underflow and generates an overflow output signal. Rounding and conversion control logic connected to the sticky output utilizes the type of conversion that has been specified and the rounding information at the sticky output for producing conversion controls at a control output and a conversion type signal output.