Abstract: An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.

Abstract: A cache controller (10) which sits in parallel with a microprocessor bus (14, 15, 29) so as not to impede system response in the event of a cache miss. The cache controller tagram (24) is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The external cache memory (8) is organized such that both ways are simultaneously available to a number of available memory modules in the system to thereby allow the way access time to occur in parallel with the tag lookup.

Abstract: An arithmetic logic for selectively multiplying either floating point numbers and unsigned integers or signed integers. A signed integer request signal has a first state indicating a floating point or unsigned integer operation and a second state indicating a signed integer operation. A multiplicand operand includes a most significant bit (MSB) of the multiplicand. A Booth encoder provides at an output of the Booth encoder a booth encoded set having a plurality of bits, including a most significant bit (MSB) of the booth encoded set. A partial product generator connected to the multiplicand operand and to the Booth encoder output generates a plurality of partial products. A carry save adder (CSA) connected to the partial product generator generates a sum vector and a carry vector. An exclusive OR has one input connected to the MSB of the Booth encoded set and another input connected to the MSB of the multiplicand. A 2:1 MUX is connected to the MSB of the Booth encoded set and to the exclusive OR.

Abstract: A scbok line is connected to a register file and other units, such as an execution unit and a multiply/divide unit, in a data processing system. A mem scbok line is connected to the register file and other units, such as an instruction unit and a memory interface unit. Each unit connected to the scbok line can pull the line to indicate that it is busy. Each unit connected to the mem scbok line can pull the line to indicate that it is busy. The scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a register file operation. The mem scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a memory operation. Registers are checked concurrently with the issuing of an instruction.

Abstract: A subsystem call mechanism for communicating between a first execution environment associated with a first domain object, and a second execution environment associated with a second domain object. An environment table object is associated with a process object. The environment table object includes a control stack which is an array of control stack entries which entries save the state of the first calling execution environment to be restored on a return from the second execution environment. A subsystem entry in the subsystem table specifies the object that defines region 2 of the target execution environment and the frame pointer of the topmost stack frame in the target environment, a supervisor Stack Pointer that is a linear address for the supervisor stack used when involving a supervisor call in the user mode (instead of the stack pointer in the current frame) to locate the new frame. The first domain object further includes Procedure Entries that specify the type and address of the target procedure.

Abstract: In a computer system having a configuration which is subject to change, because of failure replacement, updating, or expansion, it is necessary to provide means for loading parameters carrying the present system configuration into the active modules of the system. In this manner, all parallel processors are identified and recognized and depending upon system demands, used because of the parameter loading arrangement of this computer system. Serial lines are provided for loading the parameters into the active modules.

Abstract: A parallel processor comprised of a plurality of processing nodes (10), each node including a processor (100-114) and a memory (116). Each processor includes means (100, 102) for executing instructions, logic means (114) connected to the memory for interfacing the processor with the memory and means (112) for internode communication. The internode communication means (112) connect the nodes to form a first array (8) of order n having a hypercube topology. A second array (21) of order n having nodes (22) connected together in a hypercube topology is interconnected with the first array to form an order n+l array. The order n+l array is made up of the first and second arrays of order n, such that a parallel processor system may be structured with any number of processors that is a power of two. A set of I/O processors (24) are connected to the nodes of the arrays (8, 21) by means of I/O channels (106).

Abstract: An object-oriented computer architecture in which access descriptors include an object index for selecting an object in the address space, and a rights field specifying the permissible operations on a bi-paged object selected by the access descriptor. A local object lifetime bit is provided in the encoded fields portion of access descriptors, object descriptors, and page table entries to determine the lifetime of an object. The AD lifetime bit in the encoded fields of AD is compared in OTE Lifetime Check Logic with the destination object lifetime, the OTE local bit in the encoded fields of the OTE access descriptor. The OTE local bit in the encoded fields of the OTE is compared in PDTE Lifetime Check Logic with the destination object lifetime, the PDTE local bit in the encoded fields of the PDTE access descriptor.

Abstract: A tag bit is associated with each word stored in a memory. When the tag bit is a 0 the word is a data word and when a 1 the word is a valid access descriptor. Access descriptors include an object index for selecting an object in the address space of the memory, and a rights field specifying the permissible operations on a paged object selected by the access descriptor. An access descriptor in a processor control block contains a tag enable bit. An object table has stored therein object descriptors for use by an addressing mechanism in forming physical addresses to the page table object. The page table has stored therein page table entries for use by the addressing mechanism in forming physical addresses to the paged object. One of the access descriptors in a process control block contains an execution mode bit which represents either a user mode or a supervisor mode.

Abstract: Access descriptors (24) include an object index (34) for selecting an object in the address space, and a rights field (35) specifying the permissible operations on a bi-paged object (38) selected by the access descriptor. An object table (42) has stored therein object descriptors for use in forming physical addresses to the page table directory object (60) which has page table descriptors stored therein for accessing page tables. A page table (44) has stored therein page table entries for use in forming physical addresses to the paged object (38). Logic compares the page rights field (81) of the page table entry with the rights field (62) of the page table descriptor in the page table directory entry and asserts a fault if the access permitted by the page rights field (50) is inconsistent with the rights field of the access descriptor in the page table directory entry.

Abstract: Apparatus for queuing requests and replies on a pipelined packet bus. A RAM (212) buffers bus requests by storing packet information corresponding to each request to be sent over said bus in bus time slots allotted to each request. Three send slots (208) keep track of the state of three send requests that are stored in the RAM (212). Three receive slots (210) keep track of the state of three receive requests that are stored in the RAM (212). Nine send queue counters (230) are stepped through a series of states to track an outgoing request and to track a corresponding incoming reply. Six receive queue counters (232) are stepped through a series of states to track an incoming request and to track a corresponding reply. An output MUX (214) connected to the send and receive queues generates status information as to the state of the slots.

Abstract: A controller has a node interface logic (40), a ring bus interface logic (42), a set of input pins (44) and a set of output pins (45). A common logic (58) is connected to the node interface logic (40) and to the ring bus interface logic (42). The common logic includes an output FIFO buffer (32) connected to an output link interface (37) and an input FIFO buffer (34) connected to an input link interface (36). A mode select pin (43) is provided for selecting a node controller mode of operation and a ring controller mode of operation. The node interface (40) responds to assertion of the selection pin (43) to activate the pins (44, 45) with respect to the node interface (40). The ring bus interface (42) responds to deassertion of the select pin (43) to activate the pins (44, 45) with respect to the ring bus interface (42).

Abstract: A star local area network includes a ring bus hub (4) capable of being connected to a plurality of nodes (3, 5, 9) geographically distant from the hub by means of low speed serial links (18, 19, 21, 28). The nodes include processor means (2, 30, 31) for creating messages for transfer on the network. A plurality of duplex communication links (18, 19, 21, 28) connect the nodes to the ring bus hub (4). The hub (40) is comprised of a plurality of ring controllers (10, 12, 14, 16) driven by a common clock source (7). Each ring controller is connected by means of a number of parallel lines to other ring controllers in series to form a closed ring. Each one (3) of the plurality of nodes is geographically distant from the hub (4) and is connected to a corresponding one (10) of the ring controllers by means of one (18, 19) of the duplex communication links. The node controllers including node interface means (40) for transmitting the messages as a contiguous stream of words on the duplex communication link.

Abstract: A random access memory cell in a register file having multiple independent read ports and multiple independent write ports that support parallel instruction execution. The RAM cell consumes low power and conforms to a tight layout pitch to meet the needs of the random access memory. A single column line is used, with the storage latch device (M 11, M 12) increased in size to provide for the noise margin loss with reference to the prior art two-column design. A single n-device (M 1) is attached to the opposite side of the cell latch (M 11, M 12) to clear the cell prior to writing zeros into the cell. The registers that are to be written are first cleared in the PH2 of the first clock cycle, with the data written in PH1 of the second clock cycle which writes the ones. The zero bits are also written at this time, but they find a cell that already is in the zero state, having been cleared in PH2 of the first clock cycle.

Abstract: A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible.

Abstract: A ring hub in a local area network. A parallel ring bus (20, 22, 24, 26) connects a plurality of ring controllers (10, 12, 14, 16) in a closed loop. At reset time one controller (12) is selected to act as a ring monitor and is not connected to a network node. Each one of the remaining controllers are connected to a single node, so that one controller is linked to a corresponding node. The ring monitor and the ring controllers communicate by inserting message packets onto the bus and stripping messages and control information off of the bus. A transfer request packet is used by a source controller (10) to signal a destination controller (14) for permission to send a data packet. A packet acknowledge signal is generated at the destination controller (14) by asserting one of the bus control lines. The packet acknowledge signal is used to signal to the source controller that the transfer request packet has been received and placed in a request queue (40) at the destination controller.

Abstract: A computer system operative during an initialization phase to initialize modules of the system and during a subsequent non-initialization phase to transfer information between the initialized modules. A module bus (MB) has 32 signal lines beginning with a least-significant-bit signal line and ending with a most-significant-bit signal line. The bus (MB) connects the modules for data transfers after the initialization phase over bidirectional address lines and data lines connected to the module bus. A system support module (SSMI) starts the initialization phase by energizing an initialization signal line (INIT). In response, a processor (GDP) generates identification command information over the bus (MB) that continas a first data record and a second data record.

Abstract: A link (19) connects a first controller (6) and a second controller (10) in a local area network. The second controller sends a header to the first controller (6) containing status information as to the status of an input buffer (70) at the second controller. The flow of the message data from a first buffer (44) at the first controller is controlled depending upon the status of the input buffer (70) at the second node. This prevents overflow of the input buffer (70) by controlling the rate at which new messages are placed on the transmit data link (19).

Abstract: A method of up-dating a cache (10) backed by a main memory (12). The cache is used as an intermediate high-speed memory between the main memory and a data processing unit (14). A burst mode request is for multiple words (k through n) included in an m-word line of data words (1 through m). The transfer takes place by first determining if the requested data words (k through n) reside in the cache. If they do, then the requested words (k through n) are transferred from the cache to the data processing unit. If they do not, then the requested words (k through n) are transferred simultaneously from the main memory both to the cache and to the data processing unit to thereby update the cache.

Abstract: An integrated circuit module (200) in which an error detection circuit (234, 263) compares data (204) generated internally on module (200) with data (108) generated externally from another substantially identical module (100). An error detect output (238) is asserted upon the condition that data (204) generated internally on module (200) and data (108) generated externally from module (100) do not match. A circuit (222, 224) alters the internally generated data (204) by injecting erroneous data into the internally generated data (204) to thereby generate altered data (230). Error anticipation control logic (210) generates a test condition (214, 216), which corresponds to the expected error condition caused by altered data. Comparison circuit (242) compares the actual error detect output (238, 240) with expected error detect output (214, 215). An error output (244) is asserted if the actual error detect output (238, 240) and the expected error detect output (214, 216) do not match.