Abstract: A computer controlled telephone apparatus comprised of a processor controlled telephone set, apparatus for interfacing the telephone set to a telephone network, a computer for interfacing the telephone set, comprising a stored telephony service program for receiving call control signals from the apparatus for interfacing the telephone set to the telephone network, and for controlling operation of functions of the telephone set in accordance with the stored telephony service program; and monitoring apparatus in the telephone set for monitoring operation of the telephony service program and in the event there is no operation of the controlling program, for causing direct connection of the telephone set to the apparatus for interfacing the telephone set to the telephone network.

Abstract: An optical light source signal generator comprising an optical amplification medium for generating amplified spontaneous emission (ASE), having forward and backward light propagating ports for outputting output and backward optical light respectively, a reflector for reflecting the backward propagating optical light back toward the backward light propagating port, and an optical light spectrum reshaper interposed between the reflector and the backward light propagating port for transmitting the reflected light to the backward light propagating port with a wavelength dependence having a reduced amplitude in a band coinciding with an undesired high gain band of the optical amplification medium.

Abstract: An improved edge-triggered fully digital delay locked loop (DLL), which maintains reliable synchronization from startup and in spite of system clock jitter is described. An internal clock signal is synchronized with a reference clock signal by propagating the reference clock signal through a variable digital delay path. A wide phase detection region surrounds a selected rising edge of the internal clock signal. The DLL loop is open as long as the internal clock signal and a target edge of the reference clock signal are not simultaneously within the phase detection region. To achieve a DLL locked condition, the variable delay is increased from a minimum setting until the edge of the phase detection region is shifted in time just past the target edge of the reference clock. Once the DLL loop has been closed, a clock jitter filter is enabled to reject reference clock jitter effects on the DLL locked condition.

Abstract: A method of analyzing a communication network that determines a mean drop rate in a device x by polling each device from a network management computer (NMC) which is in communication with the network, and processing signals in the NMC to determine a drop rate D(x), in accordance with:D(x)=((L+(x)-L-(x))/2,and L(x)=1-A(x)whereA(x): the fraction of poll requests from the NMC to device x for which the NMC receives replies (measured over the last M sampling periods), (wherein x must not be broken),D(x): the mean frame drop rate in device x,L(c): NMC's perception of the loss rate to device x and back,L-(x): the NMC's perception of the mean value of L(z) for all devices z connected to device x, closer to the NMC than device x and which are not broken, andL+(x): the NMC's perception of the mean value of L(z) for all devices z connected to device x, further away from the NMC than device x and which are not broken.

Abstract: A ring oscillator comprising: a plurality of sub-feedback loops, each comprising a pair of serially connected inverters and a feedback inverter having its input coupled to the output of the pair of inverters and its output connected to the input of the pair of inverters, the pairs of inverters being connected in a ring, and a downstream inverter of each respective pair of inverters forming an upstream inverter of an immediately following pair of inverters.

Abstract: An address counter cell for use in burst mode operation in a synchronous DRAM is described which, in response to a falling edge of a system clock, simultaneously loads address inputs into an external address master latch and an internal address master latch, and further enables a multiplexer to select between the external and internal address inputs. In response to a subsequent rising edge of the system clock, the selected address input is then loaded into a low-output-load capacitance slave latch and is further provided to complementary output nodes. The signal from one of the output nodes is also fedback to circuitry for incrementing the selected address internally for subsequent clock cycles remaining in the burst mode operation.

Abstract: A method of routing calls, messages or information (call routing) comprising storing in a memory a database representing a relationship or organization roles, including names of persons filling the roles and call directory numbers associated with the roles, in response to a request to complete a call to a particular directory number associated with one of the roles, looking up in the database a directory number associated with one of the roles, and processing the call as if the call were directed to the further directory number.

Abstract: The invention relates to word line drivers found in embedded dynamic random access memories (DRAM) of application specific integrated circuits (ASICs). The invention is a method of programming the time at which the boosted voltage interval begins, and the period during which the boosted voltage is maintained. The result is the ability to apply the boosted voltage only when needed, thus minimizing the danger to the oxide integrity. The method comprises initiating an active row cycle in response to a leading edge of a row activation signal, initiating a precharge cycle in response to a trailing edge of the row activation signal, the precharge cycle comprising a broad line boost interval initiated by the falling edge of the row activation signal and having a predetermined duration controlled by a programmable delay circuit.

Abstract: A serial to parallel converter comprising a serial shift register for receiving an incoming serial stream of bits, a parallel word latch for receiving in parallel bits stored by the shift register, when enabled by an enable signal at an enable time, and for providing a parallel data output signal, a controller for generating an enable signal at the enable time and applying the enable signal to the parallel word latch, the controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

Abstract: A method of determining network topologies comprising monitoring traffic received by devices connected in the network and traffic emitted out of the devices, correlating traffic out of the devices with traffic into the devices, indicating a network communication path between a pair of the devices in the event that the correlation of traffic out of one of the pair of the devices and into another of the pair of the devices is in excess of a predetermined threshold.

Abstract: A method of digital to analog conversion comprising switching binary weighted groups of first current sources of a first array of sources to an output in accordance with least significant bits of a digital input signal, driving the binary weighted groups with a driving current source selected from a second group of current sources in accordance with a counter value which is based on a value of most significant bits of the input signal added to a immediately preceding counter value, and driving an output with current sources which are addressable consecutively to the driving current source.

Abstract: A hybrid method is described that allows for the combination of both source-compiled and source-interpreted code in the execution of computer programs. While traditional practice has dictated otherwise, code does not need to be either solely interpreted or solely compiled.

Abstract: A method of decrypting data comprising encrypting bit-wise data, using a first plural bit mask, modulating the data into symbol format, and transmitting the symbol format data to a receiving apparatus, in a receiving apparatus, rotating a current received symbol sample by an amount equal to one of (i) its difference in phase from an immediately preceding received symbol sample toward the phase of the immediately preceding received symbol sample phase, and (ii) by an amount equal to estimated carrier phase towards zero phase, generating a second bit mask subset derived from values of the first bit mask, comprising plural bits for each symbol, reflecting the rotated symbol by a phase defined by the plural bits to form a symbol which is devoid of encryption, and providing the symbol devoid of encryption to a soft-decision decoder.

Abstract: A gamma correction circuit comprising circuit apparatus for approximating in linear translation circuits successive nonlinear portions of a gamma correction curve, apparatus for applying an input luminance (Y) signal to the circuit apparatus, and selection apparatus for selecting signals translated by any of the circuit apparatus as a gamma corrected output signal depending on whether the input signal falls within predetermined ranges approximately corresponding to the nonlinear portions of the gamma correction curve.

Abstract: Within the field of integrated circuits used in amplifiers, a structure and improved method for calibrating a switched capacitor gain stage wherein the time required to self-calibrate a switched capacitor gain stage and the associated structure are reduced. The invention utilizes only a single calibration step which is performed while the output of the amplifier being calibrated is monitored. Instead of utilizing a plurality of capacitors C.sub.a1 --C.sub.an each in parallel with groups of trim capacitors C.sub.T, a single capacitor C.sub.a is used and connected to switches S.sub.1a1 and S.sub.1b1. Further, instead of a group of trim capacitors C.sub.T being connected in parallel with the capacitor to be trimmed, each of plurality of trim capacitors C.sub.T1 -C.sub.TN is connected between the input to the operational amplifier and a respective corresponding switch S.sub.1a2 -S.sub.1aN to the input reference voltage node V.sub.b0. As well, switches S.sub.1b2 -S.sub.

Abstract: An address counter cell for use in burst mode operation in a synchronous DRAM is described which, in response to a falling edge of a system clock, simultaneously loads address inputs into an external address master latch and an internal address master latch, and further enables a multiplexer to select between the external and internal address inputs. In response to a subsequent rising edge of the system clock, the selected address input is then loaded into a low-output-load capacitance slave latch and is further provided to complementary output nodes. The signal from one of the output nodes is also fedback to circuitry for incrementing the selected address internally for subsequent clock cycles remaining in the burst mode operation.

Abstract: An equalizer comprising a pair of high pass filters for receiving an input signal, each filter having gain, a first of the filters having gain which is substantially flat within its passband, a second of the filters having gain over a range of its passband which is controlled by an error signal, a differential amplifier for generating the error signal, having an output applied to a control input of the second filter, a pair of broadband amplitude peak detectors each for receiving an output signal of a respective one of the filters, apparatus for applying loop signals derived from outputs of the filters and passing though the peak detectors to corresponding inputs of the differential amplifier, apparatus for providing an offset to a loop signal derived from the output of the first filter, and apparatus for providing an output signal from the output of the second filter.

Abstract: A method of printing user data on a preprinted form comprising: scanning a preprinted form into a computer, and storing pixel data representing the form in a memory, indicating and storing the coordinates of data entry spaces of the scanned form, entering data into the computer at displayed locations within at least one of the indicated data entry spaces, and storing said data, inserting said preprinted form into a printer, and printing the entered data on the preprinted form within locations indicated by said coordinates.

Abstract: A method of sharing a load of incoming calls to a first automatic call distribution (ACD) system with a second ACD system, comprising: establishing at each of the first and second ACD systems divert start service levels each comprising an average wait time of incoming calls before being answered of a predetermined number of incoming calls during a sample period, monitoring a local service level at each of the ACD systems, and diverting incoming calls from one of the ACD systems to the other of the ACD systems for answering thereof in the event the local service level of the one of the ACD systems is longer than its local divert start service level.