Abstract: An electrostatic discharge circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first CMOS inverter comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the source of the second NMOS FET connected to Vss, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.

Abstract: A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.

Abstract: A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

Abstract: A method of indicating to a user of a terminal which includes a display, of the occurrence of a function which can be implemented on the terminal, comprising displaying a cursor on the display which cursor is moveable by the user and which has a form and position on the display which is related to a program currently being used by the user and which is unrelated to the function, and changing the form of the moveable cursor at the position to one which relates to the function upon occurrence of the function.

Abstract: A standby feed circuit for a subscriber line comprising a constant current power feeding circuit for a subscriber line for supplying a voltage to a subscriber line at a voltage less than a standard central office power feeding circuit, a voltage source for providing the standard voltage, apparatus for applying the standard voltage when a station apparatus connected to the subscriber line is in an on-hook condition, and apparatus for applying said voltage less than the standard voltage in place of the standard voltage when the station apparatus is in an off-hook condition.

Abstract: A first terminal for use in a time division duplex communication system comprising apparatus for automatically, successively, repetitively and alternatingly transmitting and receiving compressed signals to and from another terminal via a single transmit and receive time divided channel, including apparatus for changing a transmit and receive mode of the first terminal in synchronism with an opposite transmit and receive mode of another terminal, apparatus for receiving a timing signal which is the same timing signal received by another terminal, and apparatus for changing the mode at intervals determined from reception of the timing signal.

Abstract: A method of processing telephone calls comprising: receiving and storing a directory number of a called party with reference to a calling party, allocating a charge for the call on a billing list of a calling party, receiving a first signal from the calling party indicating a request for credit of the charge, automatically looking up data from the billing list to check against at least one predetermined criterion to determine whether the credit appears to be justified, upon receipt of the first signal, automatically applying the credit to the billing list in the event the at least one criterion is met, and automatically announcing the credit to the calling party, and automatically denying the credit in the event the at least one criterion is not met, and automatically announcing the denial to the calling party.

Abstract: A tri-state output driver comprised of a pair of complementary field effect transistors (CMOS FETs) having sources and drains connected in a series circuit between a voltage rail and ground, apparatus for applying similar logic high and low input signals to respective gates of the FETs whereby an output terminal connected in a circuit between the sources and drains of the FETs is driven toward ground or the voltage rail respectively, or opposite polarity input signals to the gates for causing the FETs to assume a high impedance, and apparatus for maintaining a voltage across the source and drain of the FET which is connected in a circuit between the voltage rail and the output terminal, at less than a lower of an FET threshold of conduction voltage or diode turn-on voltage greater than the voltage of the voltage rail, during the high impedance state, so as to maintain the latter FET in a high impedance state even when a voltage at the output terminal is equal to a voltage which is higher than an FET threshold

Abstract: A method of testing an integrated circuit chip comprised of applying to and storing a first test pattern of data on the chip, applying a second test pattern of data to the chip which corresponds to the first test pattern, comparing the stored test pattern with the second test pattern on the chip, and indicating a test fault on a test pad in the event at least one bit of the first and second test pattern differ from each other.

Abstract: A monitoring device for detecting acoustic vibrations in monitored objects has a plurality of several structure-borne sound sensors which are connected to a remote central electronic analyzing system. The individual structure-borne sound sensors are each acoustically coupled with a self-testing unit, which can be activated from the central electronic analyzing system. Activation of the self-testing units is performed by modulation of an operating voltage supplied to structure-borne sound sensors, without additional electric connections to the electronic analysis system.

Abstract: An integrated circuit test head assembly includes a group of circuit modules arranged in a circle, with the heat sinks carried by each of the modules located on the outside of the circle. The circuit modules are contained within a test head housing. Conductive pins extend downwardly from each of the modules and contact a probe card directly, without the need for an adapter. The circuit boards are cooled by flowing a cooling medium, typically a gas, around the outside of the circle of modules, so that all of the heat sinks are evenly cooled.

Abstract: A method of driving a DRAM word line comprising initiating a word line active cycle from a leading edge of a row enable signal, applying a first voltage to a word line following and as a result of said leading edge, receiving a trailing edge of the enable signal and applying a boosted voltage to the word line following and as a result of the trailing edge.

Abstract: A digital data transmission system of a type that uses NRZ line coding, comprising apparatus for generating data sequences comprising at least flag sequences and packet data, a frame generator for assembling scrambled data sequences, into frames for transmission to a receiver, and a self synchronous scrambler for continuously scrambling the data sequence including the flag sequences and packet data, and delivering the resulting scrambled data sequence to the frame generator.

Abstract: A multiported random access memory (RAM) system comprising a RAM having a data port and an address and control port, plural data buffers each having a bidirectional input port and a bidirectional output port, a data bus connecting the output ports of the data buffers and the data port of the RAM, a multiplexer having plural address and control inputs and an address and control output, the address and control output being connected to the address and control port of the RAM, each of the address and control inputs for receiving address and control data associated with data stored in a specific buffer, a timing apparatus connected to each of the buffers and to a control input of the multiplexer for separately enabling the multiplexer to pass address and control data therethrough to the address and control port of the RAM or to receive data from the data port of the RAM, whereby the bidirectional data input ports of the buffers and each of the corresponding address and control input ports forms a separate time sh

Abstract: A voltage controlled oscillator comprising: a ring of inverters comprised of an odd number of serially connected CMOS inverter stages, the inverter stages being connected between first and second oppositely poled power leads, a MOSFET having a source-drain circuit connected between one of the power leads and a first power rail, the other power lead being connected to a second power rail, apparatus for operating the MOSFET in saturation, and apparatus for applying a control voltage to the gate of the MOSFET, referenced to the second power lead, whereby the MOSFET operates as a nonlinear current conduction device having a characteristic such as to linearize the voltage-frequency characteristic of the combined MOSFET--ring oscillator combination.

Abstract: A method of searching a table stored in a memory for a record identifying a stored data word corresponding to a binary input data word, wherein the table is comprised of a plurality of records containing a select value field, a left search table address field, a right search table address field, and left and right search table address leaf fields, comprised of (a) indicating a particular single bit of the binary input data word based on a value stored in a select value field, (b) reading either the left or right search table address fields of the record containing the value stored in the first select value field, depending on the binary value of the particular single bit of the input data word indicated, (c) in the event a leaf field corresponding to the read left or right search table address stores a first binary value, repeating steps (a) and (b) using a record identified by the read left or right search table address, (d) in the event a left field corresponding to the read left or right search table addre

Abstract: A method of determining the existence of a target light source comprising progressively receiving successive pixel intensity values row by row and column by column of a scanned array of a light detector, comparing each pixel intensity value as it is received with upper and lower thresholds, declaring successive rows of pixels as dark, bright, edge or null depending on whether each row of the intensity values above, between and below the thresholds meets predetermined criteria, declaring a light source as detected in the event an array of pixels exceeding the lower threshold are completely surrounded by pixels which are of lower intensity than the lower threshold, and storing a signal indicating detection of a light source in a memory with a location identifying an address of the array in which the light source was declared as detected.

Abstract: A method of scan conversion comprising (a) receiving source data representing a predetermined signal component of respective pixels of successive lines of a non-interlaced display, (b) adding the source data related to vertically adjacent pixels in a set of source lines of the non-interlaced display to form one of an odd and even line of an interlaced display, (c) repeating step (b) for another immediately following set of source lines to form another one of the odd or even line of the interlaced display, and (d) repeating steps (a), (b) and (c) successively to an end of an odd or even field of the interlaced display.

Abstract: A method of performing a bit block transfer (Bitblt) comprised of reading a pixel data sequence from a source trajectory, writing an X coordinate portion of the pixel data sequence to a destination trajectory, repeating the writing step to the end of a scan line in the event the X coordinate portion is smaller than the scan line, reset the X coordinate following the end of the scan line, reset a Y coordinate and write a successive X coordinate portion of the pixel data sequence to the destination register from an X coordinate start position when the Y coordinate actually advances in the pixel data sequence.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.