Abstract: The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.

Abstract: A method of processing audio signals is comprised of reading samples of digitally stored audio signals from a first source memory, performing a bit block transfer (BitBLT) of the samples to a register of an arithmetic and logic unit (ALU), reading an array of coefficient signals (coefficients), performing a BitBLT of the coefficients to a register of the ALU, operating on the bit block transferred samples and coefficients together and storing resulting samples in a destination memory, whereby the stored resulting samples can be further accessed for audio reproduction, further processing, permanent storage or transmission.

Abstract: A method of management of resources in a multiple process system providing a list of resource owner identities, storing in an owner list the identity of at least one process with a resource which the at least one process has a right to operate, and allowing only a process listed with a resource to use the resource.

Abstract: A deployable antenna system comprised of a pair of independently flexible membranes carrying elements of the antenna system, apparatus fixed to corresponding extremity locations of the membranes for stretching the membranes taught and flat, spacers rigidly fixed to corresponding facing locations on the membranes, the locations being selected such that a line passing through each of the spacers is orthogonal to the surface of the membranes when the membranes are stretched, and at another angle to the surface when the membranes are either relaxed or one membrane is shifted laterally to the other.

Abstract: A delay line having variable delay comprising apparatus for receiving an input clock signal and for providing an inverted and non-inverted version thereof, a plurality of serially connected inverter stages each for receiving and translating the inverted and non-inverted versions of the input clock signal, inverted and non-inverted outputs of each of the inverter stages except a last inverter stage in series being cross-connected to inputs of an immediately following inverter stage, and apparatus for shunting outputs of one of the inverter stages to a pair of output nodes.

Abstract: A method of silent monitoring in a telephone system by a monitor comprising storing in a first table in a memory, correspondence between an agent identifier and a telephone set directory number used by the agent, requesting silent monitoring of the agent using the identifier, checking the table to determine the directory number of the telephone set corresponding to the agent, creating and storing a record containing the directory number, an identifier of the monitor and the agent identifier, in the event a telephone call is in process using the telephone set, conferencing a telephone set used by the monitor with the telephone set used by the agent, using a one way audio path toward the telephone set used by the monitor, in the event the telephone call in process clears, maintaining the record until the telephone set used by the monitor has gone on-hook, and continuing to monitor subsequent calls involving the telephone set used by the agent prior to the telephone set used by the monitor going on-hook, maintai

Abstract: The present invention relates to an image scaler comprised of apparatus for receiving coefficients a and b and image display values of adjacent pixels P and Q respective of an image, apparatus for repeatedly operating on the coefficients and values for successive pixels according to the transform ##EQU1## where SUM is the sum of the coefficients,R is either zero or the accumulated SUM of an immediately preceding operation,A.sub.cc is an accumulated result signal, and apparatus for providing a first result signal as an output coefficient word for controlling the display of each of adjacent pixels.

Abstract: A capacitive pressure transducer comprising a first capacitor having a plate which is movable under the influence of pressure and a fixed plate, and a second capacitor having a pair of fixed plates, one plate of the second capacitor and the fixed plate of the first capacitor being fixed to a common support, a first structure for moving the movable plate, a support structure for a second plate of the second capacitor, masses of the support structure for the second plate and of the first structure for moving the movable plate being approximately equal.

Abstract: A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

Abstract: A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

Abstract: A random access memory comprising rowlines and columns crossing the rowlines, memory cells being associated with crossings of rowlines and columns; apparatus for connecting the memory cells to columns from voltage carried on the rowlines, the rowlines, columns and memory cells being arranged in more than two adjacent arrays; a column decoder providing access apparatus to columns in all the arrays; apparatus to disable the column access in any or all arrays and apparatus to enable a replacement spare column or columns using a spare column decoder in any or all of the arrays.

Abstract: A method of repeating a pulse signal comprised of outputting a signal at a first voltage level upon a first rising edge of the pulse signal exceeding a low threshold, then raising the threshold and outputting the signal at another voltage level upon a second trailing edge of the pulse signal dropping below the raised threshold. An improved VLSI circuit has at least one conductive track containing distributed parasitic elements, the track being divided into two or more separate segments, a repeater connecting each of the segments, and apparatus for modulating the threshold of the repeater prior to and/or during the interval of a pulse carried by the track.

Abstract: A phase locked loop is comprised of a phase-frequency detector for providing to a charge pump up and down pulse signals having pulse widths proportional to phase differences between a pair of signals applied thereto, apparatus for introducing a relative phase difference between a first clock signal and a second signal to provide the pair of signals, the second signal being synchronized with an output signal of the loop, apparatus for providing a third up or down signal to the charge pump offsetting the effect of the introduced phase difference, and apparatus for obtaining a loop control voltage from the charge pump.

Abstract: A DRAM charge storage structure including of a p-channel access FET in an n.sup.- doped well of a p.sup.- doped substrate, a p.sup.- channel charge storage capacitor, conductive apparatus connecting a gate of the charge storage capacitor to a drain of the FET, and apparatus for applying a boosted word line voltage to a gate of the FET.

Abstract: A method of communicating with peripheral devices via a personal computer parallel port having computer data bus lines but no address bus lines comprising connecting the input of a multiplexer to the parallel port, the multiplexer having a data bus input and a databus output and an address bus output, applying address data to the computer data bus, applying an address control signal to the multiplexer and passing the address data only to the address bus output as a result thereof.

Abstract: An electrical bridge for communicating signals to or from an organ or a patient comprising a non-porous, non-metallic, flexible tubular duct, an ionically conductive liquid contained in the duct for transmitting electrical signals by ion transfer and a non-metallic conductive plug at an end of the duct for electrically connecting to the organ or patient.

Abstract: A power up, power down reset circuit formed of charge storage apparatus for receiving and storing charge from one pole of a voltage supply, a pair of complementary field effect transistors having source-drain circuits connected in series aiding direction between the charge storage apparatus and another pole of the voltage supply, apparatus for connecting the one pole of the voltage supply to a gate of one transistor of the pair of transistors, apparatus for applying a voltage derived from the one pole of the voltage supply but having a value reduced from voltage of the voltage supply, to a gate of another transistor of the pair of transistors, and apparatus for providing a reset pulse from a junction between the source-drain circuits of the pair of transistors.

Abstract: A voltage controlled oscillator comprised of a current controlled oscillator formed of a loop of serially connected inverters, the oscillator having a primary output at an output of one of the inverters for providing a primary pulse signal and a secondary output at the output of another inverter spaced from the one inverter by an odd number of inverters for providing a secondary pulse signal which is in antiphase to the primary pulse signal, apparatus for receiving the primary and secondary pulse signals and for providing an output signal which indicates the presence of a rising or falling edge to a corresponding primary or secondary pulse signal during a transmission time delay provided by the odd number of inverters.

Abstract: An electronic circuit board enclosure comprised of a planar member having dimensions at least equal to dimensions of the circuit board, first pillars fixed to at least one side of the planar member and extending orthogonally to the planar member above the planar member, apparatus for aligning and fixing bottoms of second pillars of another circuit board enclosure to tops of the first pillars, apparatus for fastening a first circuit board to and above the planar member, and locating apparatus for precisely locating the fastening position of the circuit board to the planar member relative to the first pillars, whereby the position of the first circuit board can be located precisely relative to another circuit board fastened to another circuit board enclosure.

Abstract: A helical antenna comprised of a helical conductor having one end adapted to be connected to a feedline, a conductive surface contained within but spaced from the helical conductor, the distance of the conductive surface from the helical conductor being predetermined so as to vary the radiation loss from the helical conductor during electromagnetic emission therefrom.