Patents Represented by Attorney, Agent or Law Firm Patrick T. King
  • Patent number: 5444921
    Abstract: An apparatus and method for determining the distance of a semiconductor wafer from a nozzle of an edge bead removal system. A rotationally adjustable gap gauge is placed over a vacuum chuck of an edge bead removal system. The gap gauge has a ramped surface which is located proximate to the nozzle when the gap gauge is placed over the vacuum chuck. By rotating the gap gauge on the vacuum chuck, the ramped surface is brought closer to the nozzle. When the nozzle contacts the ramped surface, the position of the gap gauge, as shown by calibration marks on the gap gauge, are recorded. The calibration marks on the gap gauge indicate the corresponding distance that will exist between the nozzle and the backside of a semiconductor wafer when the gap gauge is removed and a semiconductor wafer is placed onto the vacuum chuck. The edge bead removal system is then adjusted such that a desired distance will exist between the nozzle and a semiconductor wafer when a semiconductor wafer is placed onto the vacuum chuck.
    Type: Grant
    Filed: February 2, 1994
    Date of Patent: August 29, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Daniel V. Milina
  • Patent number: 5442234
    Abstract: A molded plastic package for an integrated-circuit die includes a lead frame having a central die-attach paddle. One side of the die-attach paddle has an integrated-circuit die fixed thereto. A heat sink member is resiliently fixed to the other side of the die-attach paddle using a layer of viscous thermal grease between the heat sink member and the other side of the die-attach paddle. One or more holes are formed in the lead frame and are engaged by corresponding studs on the heat sink. The stud has a shoulder portion which engages the lead frame to prevent the stud from further passing through the hole in the lead frame.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: August 15, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Louis H. Liang
  • Patent number: 5440715
    Abstract: Apparatus and a method for easily expanding the effective width of the data words of a CAM without significantly increasing the basic width of the data storage registers or comparand register. A plurality of comparison blocks each include a register for data words having a predetermined width. Each data word includes a start bit, which indicates that a data word is the first data word of a much larger data word (or data line), and a chain bit, which indicates that a match has occurred between part of a comparand and the data word stored in the register. A maskable comparator provides a match output signal. The start bit is initially loaded into the chain-bit register for a data word. A latch is provided for storing the value of the chain bit from a preceding register into the chain-bit register of a following register. A priority encoder receives the match output signals from each of the comparators of the comparison blocks to identify the highest-priority comparison block, and the corresponding data line.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: August 8, 1995
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David C. Wyland
  • Patent number: 5437457
    Abstract: A golf simulator is provided with an improved trajectory sensing and spin detector. The trajectory sending system includes a first row of light sensors located adjacent to a tee and receiving light from a first light source directly above the tee. Second and third rows of light sensors are positioned away from the tee. The second row receives light from a second source directly overhead. The third row receives light from the first light source where a plane of light is defined between the first light source and the third row of sensors. The time intervals between a golf ball passing from the tee to the first plane of light and to the second plane of light, where the second plane of light is defined by the second light source and the second row of sensors are detected by the first, second, and third rows of light sensors. The angle of elevation of a golf ball is determined as a function of the ratio of the first and second time intervals.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: August 1, 1995
    Assignee: Virtual Golf, Inc.
    Inventor: Donald B. Curchod
  • Patent number: 5434417
    Abstract: An apparatus and method for detecting an x-ray and for determining the depth of penetration of an x-ray into a semiconductor strip detector. In one embodiment, a semiconductor strip detector formed of semiconductor material is disposed in an edge-on orientation towards an x-ray source such that x-rays From the x-ray source are incident upon and substantially perpendicular to the front edge of the semiconductor strip detector. The semiconductor strip detector is formed of a plurality of segments. The segments are coupled together in a collinear arrangement such that the semiconductor strip detector has a length great enough such that substantially all of the x-rays incident on the front edge of the semiconductor strip detector interact with the semiconductor material which forms the semiconductor strip detector. A plurality of electrodes are connected to the semiconductor strip detect or such that each one of the of semiconductor strip detector segments has at least one of the of electrodes coupled thereto.
    Type: Grant
    Filed: November 5, 1993
    Date of Patent: July 18, 1995
    Assignee: The Regents of the University of California
    Inventor: David R. Nygren
  • Patent number: 5430331
    Abstract: An integrated-circuit die attached to a thermally conductive substrate having surface variations formed into the surface of the thermally conductive substrate. A lead frame has inwardly-extending fingers, which are attached to the thermally conductive substrate. The integrated circuit die, lead frame, and substrate are enclosed within a mold cavity. The surface variations of the thermally conductive substrate provide for a more balanced flow of plastic material over the top and bottom of the substrate provide a molded package body substantially free of voids.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: July 4, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Ahmad Hamzehdoost, Sang S. Lee
  • Patent number: 5430250
    Abstract: Single, continuous bonding wires for an integrated-circuit die are supported in mid-span by a support ring which is snap-fit or adhesively bonded to a die-attach paddle of a leadframe. The support member includes a groove formed in its distal end for receiving an adhesive material, if necessary, for securing the bonding wires in position to prevent wire-wash and electrically shorting of the bonding wires when a plastic molding compound is formed around the die and leadframe. Alternatively the bonding wires are contained within notches formed in the distal end of the support ring. A lid placed over the support ring provides an enclosure for the integrated-circuit die. Stacking of support rings on each other and concentric support rings provide various optional arrangements for supporting bonding wires.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: July 4, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5424638
    Abstract: An apparatus and method for detecting defects in the magnetic medium of a disk drive system includes sampling the output signal of the read channel of the system to provide a sampled output signal. In one embodiment, the sampled output signals from the read channel is squared. A delayed sampled output signal is also provided. The squared sampled output signal is summed with the delayed squared output signal. The square of the expected value of the sum of the squared sampled output signal and the delayed squared output signal is subtracted from the sum to provide a difference output signal. A threshold detector determines when the difference output signal of the subtraction means exceeds a predetermined threshold to provide an output signal indicative of a defect in the medium. One threshold detector determines when the absolute value of the difference output signal exceeds a predetermined threshold value.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: June 13, 1995
    Assignee: Seagate Technology, Inc.
    Inventor: William D. Huber
  • Patent number: 5420758
    Abstract: An integrated-circuit package assembly including a lead frame having a number of inwardly extending fingers, the alternate ends of which are formed into an upper row and a lower row to provide a space there between for receipt of the outer edges of a multi-layer printed circuit board (PCB). Vias formed adjacent to the outer edges of the PCB engage with corresponding alternate ends of the inwardly extending fingers when the edges of the multi-layer PCB are inserted in the space provided between the row of fingers in the upper plane and the row of fingers in the lower plane. The ends of the inwardly extending fingers have various lengths which engage via contact pads formed on opposite surfaces of the PCB. A group of the fingers can be pivoted to open the space between the upper and lower row of fingers.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: May 30, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Louis H. Liang
  • Patent number: 5418486
    Abstract: A noise-suppression logic system suppresses a noise signal having a time duration which is less than a predetermined time. A delay circuit has a delay which is equal to the predetermined time. A logic combining circuit is coupled to the system input terminal and to the output terminal of the delay circuit. A R-S latch circuit, having a RESET input terminal, a SET input terminal, and an OUTPUT terminal provides a delayed output signal corresponding to an input signal which has a time duration greater than the predetermined time. A set circuit has a first input terminal coupled to the system input terminal, a second input terminal coupled to the output terminal of the delay circuit, and an output terminal coupled to the SET input terminal of the R-S flip-flop circuit.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: May 23, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: John M. Callahan
  • Patent number: 5412250
    Abstract: An improved barrier, and a method for forming such a barrier, between a semiconductor substrate and a metallized contact. A first metallic layer is deposited over the substrate and the contact well formed therein. The first metallic layer is then exposed to a gas to allow the gas to stuff the first metallic layer, thereby improving the barrier characteristics of the first metallic layer. A second metallic layer is deposited over the first stuffed metallic layer. A third metallic layer is then deposited over the second metallic layer. An anti-reflective fourth layer of metal is then deposited over the third metallic layer. The exposure of the first metallic layer to a gas and all of the metal layer deposition steps are performed in a low-pressure environment. Therefore, the present invention eliminates the need for time-consuming pressure breaks. As a result, the throughput of the present invention is substantially increased over prior art barrier formation processes.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: May 2, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Hunter B. Brugge
  • Patent number: 5405813
    Abstract: A method and process for reducing the amount of photoresist material required to uniformly coat a semiconductor wafer. A semiconductor wafer, having a top and a bottom surface, is placed onto a vacuum chuck of a photoresist coater system for applying photoresist to semiconductor wafers such that the semiconductor wafer is oriented in horizontal plane with the top surface of the semiconductor facing upwards. The vacuum chuck of the wafer coating system is rotated about a central axis thereof such that the semiconductor wafer achieves a first rotational speed. Next, the semiconductor wafer is decelerated from the first rotational speed to a second rotational speed while a minimal amount of photoresist material is concurrently dispensed onto the top surface of the semiconductor wafer. As the wafer reaches the second rotational speed, the dispensing of the photoresist material onto the top surface of the semiconductor wafer is stopped.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: April 11, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Michael A. Rodrigues
  • Patent number: 5399508
    Abstract: A self-aligned MOSFET incorporating a punchthrough implant, and the method for forming such a transistor. A dielectric layer is used as a hard mask over a semiconductor substrate. A portion of the dielectric layer is removed to expose a region of the semiconductor substrate. A punchthrough implant is made with the remaining portion of the dielectric layer acting as a mask layer such that the doping concentration is raised by the punchthrough implant only in the exposed region of the semiconductor substrate. A doped layer of polysilicon is formed over the region into which the implant was made to provide a self-aligned gate over the highly doped region. A source and drain are formed on opposite sides of the doped region. A protective layer is formed over the device and metallized contacts are formed to the source, drain, and gate.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: March 21, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Edward D. Nowak
  • Patent number: 5391513
    Abstract: An improved method for forming vias in an anti-fuse semiconductor device through an oxide layer to an underlying metallic layer. A wet etch is performed on the oxide layer at selected regions where vias are to be formed. The wet etch is controlled such that a first recessed area is formed in the oxide layer at the selected regions. The first recessed area formed by the wet etch extends only partially through the oxide layer towards the underlying metallic layer. Additionally, the first recessed area is formed having a smoothly shaped contour. Next, a dry etch is performed on the oxide layer at the selected regions where the vias are to be formed. The dry etch is performed within the first recessed area. The second recessed area has a smaller cross sectional area than the first recessed area such that the second recessed area is peripherally bordered by the first recessed area.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: February 21, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Miguel A. Delgado, Stacy W. Hall
  • Patent number: 5388101
    Abstract: In a two-way interactive communication video network having a network switching center for point-to-point communications between subscribers at different geographic locations, a local base station configuration is provided for facilitating low power battery operated portable subscriber units. The local subscriber units surrounding a base station are adapted for multiplex transmission of digital messages synchronously related to a broadcast television signal for system coordination. Digital messages are transmitted from the local subscriber units to the base station data processing facility through a set of receive only cell site subdivision zones distributed over the base station transmitter geographical range, which communicate with the base station data processing facility over a communication link such as wired cable. Messages are compiled and relayed by satellite to a network switching center transmitter site for nationwide point-to-point communications.
    Type: Grant
    Filed: October 26, 1992
    Date of Patent: February 7, 1995
    Assignee: Eon Corporation
    Inventor: Gilbert M. Dinkins
  • Patent number: 5388074
    Abstract: A FIFO memory circuit with improved read-access time includes an output register, which is connected to the data output terminal of the FIFO. The output register is clocked to provide the output of the FIFO with only the clock-to-output delay of the register. The FIFO memory circuit is formed with a series of latches, each of which latch has a data-input terminal connected in parallel to the data input terminal of the FIFO. Each latch has a tri-state output which is connected to an output terminal for the FIFO. Write-pointers select the next-available one of the FIFO locations to be read into. Read pointers select the next FIFO location to be read from. An input storage register is also provided to improve the input access time of the FIFO.
    Type: Grant
    Filed: December 17, 1992
    Date of Patent: February 7, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Karl C. Buckenmaier
  • Patent number: 5387554
    Abstract: A molded plastic package for an integrated-circuit die includes a lead frame having a central die-attach paddle. One side of the die-attach paddle has an integrated-circuit die fixed thereto. A heat sink member is resiliently fixed to the other side of the die-attach paddle using a layer of viscous thermal grease between the heat sink member and the other side of the die-attach paddle. One or more holes are formed in the lead frame and are engaged by corresponding studs on the heat sink. The stud has a shoulder portion which engages the lead frame to prevent the stud from further passing through the hole in the lead frame.
    Type: Grant
    Filed: July 23, 1993
    Date of Patent: February 7, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Louis H. Liang
  • Patent number: 5386141
    Abstract: Power and ground connections are provided using or more conductive layers provided in an integrated-circuit package design. A leadframe has either a tape assembly or a heat-conducting dielectric ceramic substrate attached to the die-attach paddle of the leadframe and one or more conductive planes are formed on the top surface of the tape assembly or the ceramic substrate. The tape assembly includes a conductive metal layer, a polyimide layer, and an adhesive layer. The metal layer on the tape or ceramic substrate and the metal die-attach pad of the leadframe are used as low inductance power planes providing connections to the integrated-circuit. No vias are used. Use of a metal die-attach paddle for the leadframe is optional when a ceramic substrate is used.
    Type: Grant
    Filed: March 31, 1992
    Date of Patent: January 31, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Louis H. Liang, Tsing-Chow Wang
  • Patent number: 5378924
    Abstract: A molded plastic package for an integrated-circuit die includes a lead frame having inwardly extending tie bars and a central die-attach paddle. One side of the die-attach paddle has an integrated-circuit die fixed thereto. A heat sink member is resiliently fixed to the other side of the die-attach paddle using a layer of viscous thermal grease between the heat sink member and the other side of the die-attach paddle. At least one holes is formed through a portion of the lead frame and is engaged by a corresponding elongated stud on the heat sink. The elongated stud extends upwardly through the layer of thermal grease through the holes in the lead frame and terminates at the top of the molded plastic package. By extending to the top of the plastic package, the elongated stud firmly holds the heat sink against the bottom of the mold cavity during the encapsulation process. As a result, the bottom surface of the heat sink remains exposed after the encapsulation process.
    Type: Grant
    Filed: July 23, 1993
    Date of Patent: January 3, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Louis H. Liang
  • Patent number: 5379187
    Abstract: An improved packaging technique for packaging a thermally-enhanced, molded-plastic quad flat package (TE-QFP). An integrated-circuit die is attached to a thermally conductive, electrically-insulated substrate having a stepped area formed into the outer margins thereof. A lead frame has inwardly-extending fingers, which are attached to the stepped areas in the outer margins of the thermally conductive, electrically-insulated substrate. The stepped area centers the thermally conductive, electrically-insulated substrate and attached integrated-circuit die within the mold cavity so that the flow of plastic material is balanced over the top and bottom of the substrate to provide a molded package body substantially free of voids.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: January 3, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Sang S. Lee, George Fujimoto