Abstract: A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed over the thin film resistor (55). Metal structures (120 are formed above the thin film resistor (55) and metal (110) is used to fill a trench and via formed in the dielectric layer (80).

Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).

Abstract: A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor wafer through orifices (100) containing in the ring (70). Water and/or nitrogen can be applied to the surface of the semiconductor wafer through orifices (110) contained in the spokes (90).

Abstract: An integrated circuit resistor (170) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (125) and an optional patterned silicon oxide layer (135) is formed on the surface of the resistor polysilicon layer (40) that functions to mask the surface of the integrated circuit resistor (170) during the formation of metal silicide regions (160) on the integrated circuit resistor (170).

Abstract: An integrated semiconductor system is provided that is formed on a substrate 10. A dual implant mask 26 is used to change the characteristics of semiconductor devices formed in regions of the substrate 10 having different characteristics. Transistors 50 and 52 can be formed on the same substrate 10 and have different electrical characteristics.

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.

Abstract: An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from the active region 22 by extension zones 27a and 27b. The spacing is established by using an inner mask layer 20 and an outer mask layer 26 to define the isolation structures.

Abstract: An integrated circuit resistor (150) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (74) is formed on the surface of the resistor polysilicon layer (40) that functions to mask the surface of the integrated circuit resistor (150) during the formation of metal silicide regions (140) on the integrated circuit resistor (150).

Abstract: A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor defines a channel region disposed inwardly from the gate conductor. Source and drain regions are formed in the semiconductor substrate, each disposed adjacent one edge of the channel region. The semiconductor substrate and the source and drain regions have an associated bottom wall junction capacitance. A transient enhanced diffusion anneal is used to affect ion concentration profiles associated with the source and drain regions, resulting in an increased balance in the ion concentration profiles of the source and drain regions and an ion concentration associated with the semiconductor substrate, which results in reduction of the bottom wall junction capacitance.

Abstract: According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.

Abstract: A method of forming a semiconductor device using shallow trench isolation, includes forming a trench within a semiconductor substrate and forming a screen dielectric stack outwardly from the semiconductor substrate. The screen dielectric stack includes a first sacrificial dielectric layer disposed outwardly from the semiconductor substrate and a second sacrificial dielectric layer disposed outwardly from and in contact with the first sacrificial dielectric layer. In one embodiment, the first sacrificial dielectric layer is formed before forming the trench and the second sacrificial dielectric layer is formed after forming the trench.

Abstract: An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage Vt. The implant provides independently tuned either NMOS core transistors and I/O transistor Vth or PMOS core transistors and I/O transistor Vth.

Abstract: According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilicon layer, and forming an emitter region by removing a portion of the dielectric layer and a portion of the base polysilicon layer. The method further includes removing a portion of the first oxide layer to form undercut regions adjacent the emitter region and to enlarge the emitter region, and forming an oxide pad outwardly from the semiconductor substrate in the emitter region.

Abstract: The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material (116) into the semiconductor wafer, implanting a halo material (110) into the semiconductor wafer (102), selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the semiconductor wafer at the selected dose and energy, activating the dopant material using a thermal process and annealing the semiconductor wafer to remove residual fluorine. The one or more characteristics of the transistor may include halo segregation, halo diffusion, the sharpness of the halo profile, dopant activation, dopant profile sharpness, drive current, bottom wall capacitance or near edge capacitance.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions.

Abstract: A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method also includes implanting a halogen species in the amorphous region of the at least partially formed semiconductor device. The method further includes doping at least a portion of the at least one amorphous region to form at least one junction within the at least partially formed semiconductor device. The method also includes performing solid phase epitaxial re-growth to activate the doped portion of the at least one amorphous region of the at least partially formed semiconductor device.

Abstract: Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of the substrate material during deposition of the oxide layer, thereby avoiding or mitigating formation of low-k interfacial layer.

Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.