Abstract: The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

Abstract: The method for removing particles that adhere to the surface of semiconductor wafers is constituted so as to sequentially carry out a first cleaning process in which semiconductor wafers 100 are cleaned for a prescribed time in cleaning tank 104 containing a first cleaning solution consisting of ozone water, and, after said first cleaning process, a second cleaning process in which said semiconductor wafers 100 are cleaned for a prescribed time in cleaning tank 106 containing a second cleaning solution consisting of hydrogen water.

Abstract: The instant invention is a method for forming a smooth interface between the upper surface of a silicon substrate and a dielectric layer. The invention comprises forming a thin amorphous region (180) on the upper surface (170) of a silicon substrate prior to forming the dielectric layer on the upper silicon surface.

Abstract: The present invention defines a versatile system for analyzing accuracy of industrial measurement data. The system of the present invention compiles measurements of a primary device characteristic from a representative cross-section of a population of devices. The system provides a modeling function, from which is determined a variance for each measurement—forming a corresponding compilation of variances (200). The compilation of variances is evaluated for discontinuities (300), to identify a discontinuity within the compilation of variances. This discontinuity is utilized to determine a demarcation (302) between accurate and inaccurate measurement data.

Abstract: The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (40). The tantalum nitride films are selectively removed using an oxidizing plasma chemistry.

Abstract: Generating an optical model includes receiving lens aberration data associated with a wafer response to lens aberrations. Aberration functions are selected and fit to the lens aberration data. An optical model is generated in accordance to the aberration functions, where the optical model indicates the wafer response to the lens aberrations.

Abstract: The instant invention describes a method for forming a dielectric film with a uniform concentration of nitrogen. The films are formed by first incorporating nitrogen into a dielectric film using RPNO. The films are then annealed in N2O which redistributes the incorporated species to produce a uniform nitrogen concentration.

Abstract: A method for preparing a sample includes separating a portion of substrate from a sample, performing focused ion beam milling, and removing additional sample material using an etchant.

Abstract: According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a dielectric layer. The method also includes forming a layer of metal in direct contact with the dielectric layer. The method also includes directly exposing the layer of metal, after forming the layer of metal, to plasma at a power level sufficient to penetrate through the layer of metal and reach the dielectric layer.

Abstract: The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etching 250 through a patterned hardmask layer 210 located over a semiconductor substrate 225 wherein the plasma etching forms a modified layer 210a on the hardmask layer 210, and removing at least a substantial portion of the modified layer 210a by exposing the modified layer 210a to a post plasma clean process.

Abstract: An electrostatic discharge (ESD) protection structure for protecting against ESD events between signal terminals is disclosed. ESD protection is provided in a first polarity, by a bipolar transistor (4C) formed in an n-well (64; 164), having a collector contact (72; 172) to one signal terminal (PIN1) and its emitter region (68; 168) and base (66; 166) connected to a second signal terminal (PIN2). For reverse polarity ESD protection, a diode (25) is formed in the same n-well (64; 164) by a p+ region (78; 178) connected to the second signal terminal (PIN2), serving as the anode. The cathode can correspond to the n-well (64; 164) itself, as contacted by the collector contact (72; 172). By using the same n-well (64; 164) for both devices, the integrated circuit chip area required to implement this pin-to-pin protection is much reduced.

Abstract: A gate structure (30) is formed on a semiconductor (10). Source and drain extension regions (130) are formed in the semiconductor (10) adjacent to the gate structure (30). Metal silicide layers (140) are formed on the extension regions (130) and sidewall structures (155, 165, and 175) are formed over the metal silicide layers (140). Source and drain regions (120) are formed in the semiconductor (10), and metal silicide layers (180) are formed on the source and drain regions (120).

Abstract: The present invention discloses a polishing pad that can facilitate process stability, extend length of use, and mitigate process non-uniformity and process induced defects for chemical mechanical planarization processes. The polishing pad of the present invention is a composite of a top pad and a sealed sub-pad. The sealed sub-pad has a sealing mechanism that mitigates liquid penetration into the sub-pad thereby maintaining a substantially uniform compressibility of the sub-pad and the polishing pad and extending a useable life of the polishing pad.

Abstract: A system and method for detecting a milling endpoint on a semiconductor sample by directing an ion beam from a focused ion beam (FIB) apparatus at the sample and using charge pulse detection electronics (CPDE) components to generate a distribution curve on a histogram display. A preferred configuration of the CPDE components includes a charge preamplifier, a pulse amplifier, a pulse shaper, and a multichannel analyzer (MCA).

Abstract: A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.

Abstract: A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).

Abstract: Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

Abstract: A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

Abstract: Light is incident on a semiconductor wafer polish surface and an adjacent reference surface (80). The reflected light from each surface is detected by a detector (35) positioned beneath the surfaces. The signals derived from each source of reflected light is analyzed in a electronic system (37) and an endpoint for a chemical mechanical polish process is determined as a function of both signals.

Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).