Patents Represented by Attorney, Agent or Law Firm Peter K. McLarty
  • Bipolar junction transistor with a counterdoped collector region
    Patent number: 6894366
    Abstract: An improved BJT is described that maximizes both Bvceo and Ft/Fmax for optimum performance. Scattering centers are introduced in the collector region (80) of the BJT to improve Bvceo. The inclusion of the scattering centers allows the width of the collector region WCD (90) to be reduced leading to an improvement in Ft/Fmax.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 17, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory E. Howard, Jeffrey Babcock, Angelo Pinto, Scott Balster
  • Method for manufacturing a bipolar junction transistor
    Patent number: 6887765
    Abstract: According to one embodiment of the invention, a method used in manufacturing an intermediate structure in a bipolar junction transistor includes implanting a base dopant in a semiconductor substrate to form a base, forming a dielectric layer outwardly from the semiconductor substrate, etching a portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and after forming the emitter polysilicon layer, annealing the semiconductor substrate.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: May 3, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory E. Howard, Angelo Pinto
  • Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same
    Patent number: 6885054
    Abstract: The present invention provides a threshold voltage stabilizer for use with a MOS transistor having a body effect associated therewith. In one embodiment, the threshold voltage stabilizer, includes a body well located in a substrate, a source located in the body well, and a stabilization region positioned below the body well. The threshold voltage stabilizer is configured to provide a stabilization voltage to the stabilization region to increase a depletion region within the body well and thereby restrict the body effect to stabilize a threshold voltage of the MOS transistor.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: April 26, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Pinghai Hao, Imran M. Khan
  • Method of manufacturing and structure of semiconductor device with floating ring structure
    Patent number: 6884686
    Abstract: A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor device also includes a floating ring structure disposed inwardly from at least a portion of the field oxide layer. In one particular embodiment, a device parameter degradation associated with the semiconductor device comprises one (1) percent or less after approximately five hundred (500) seconds of accelerated lifetime operation.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: April 26, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Sameer P. Pendharkar
  • Reduced size plate layer improves misalignments for CUB DRAM
    Patent number: 6873001
    Abstract: In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: March 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Toshiyuki Nagata, Hiroyuki Yoshida, Masayuki Moroi, Atsushi Satoh
  • Method of forming an integrated circuit thin film resistor
    Patent number: 6872655
    Abstract: A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias (110) are formed in the capping layer (90) using a two step etching process comprising of a dry etch process and a wet etch process. Conductive layers (120) are formed in the vias and form electrical contacts to the thin film resistor structure (75).
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: March 29, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Pushpa Mahalingam, Robert Hung Nguyen, Philipp Steinmann, Eric W. Beach, Siang Ping Kwok
  • System and method for measuring a capacitance associated with an integrated circuit
    Patent number: 6870375
    Abstract: A method for measuring a capacitance associated with a portion of an integrated circuit is provided that includes coupling a measurement circuit to an integrated circuit. One or more transistors within the integrated circuit are initialized such that a steady-state associated with one or more of the transistors is achieved. A capacitance associated with the portion of the integrated circuit is then measured using the measurement circuit. The portion of the integrated circuit is selectively charged and discharged in response to a voltage potential being applied thereto such that a drain current is generated that serves as a basis for the capacitance measurement.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: March 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Robin C. Sarma, Xiaowei Deng, James David Gallia
  • Method for improving a physical property defect value of a gate dielectric
    Patent number: 6869862
    Abstract: The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: March 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Brian K. Kirkpatrick, Mercer Brugler, Eddie Breashears, Jon Holt, Corbett Zabierek, Rajesh Khamankar
  • Series feram cell array
    Patent number: 6867997
    Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: March 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Katsuo Komatsuzaki
  • System for high-precision double-diffused MOS transistors
    Patent number: 6867100
    Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: March 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland
  • Measurement of wafer temperature in semiconductor processing chambers
    Patent number: 6864108
    Abstract: A coil (50) is placed adjacent to a semiconductor wafer (10). An AC excitation current is used to create a changing electromagnetic field (60) is the wafer (10). The wafer is heated by a heat source (20) and the conductivity of the wafer (10) will change as a function of the wafer temperature. Induced eddy currents will cause the inductance of the coil (50) to change and the temperature of the wafer (10) can be determined by monitoring the inductance of the coil (50).
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: March 8, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Satyavolu S. Papa Rao, Stephan Grunow, Noel M. Russell
  • JFET structure for integrated circuit and fabrication method
    Patent number: 6861303
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide
    Patent number: 6858908
    Abstract: A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the semiconductor surface. Further, the method forms a first transistor gate electrode (902) comprising a metal portion (402) in a fixed relationship with respect to the gate dielectric. Still further, the method forms a second transistor gate electrode (901) comprising a silicide (701) of the metal portion in a fixed relationship with respect to the gate dielectric.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: February 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Mark R. Visokay
  • System and method for measuring a capacitance of a conductor
    Patent number: 6856143
    Abstract: A method for measuring a capacitance of a device under test is provided that includes selectively charging and discharging a first conductor with a first set of p and n element-pairs in response to a voltage potential applied to the first set of p and n element-pairs. The method further includes selectively charging and discharging a second conductor with a second set of p and n element-pairs in response to a voltage potential applied to the second set of p and n element-pairs. Currents are measured at drains associated with the first set of p element-pairs as the first and second conductors charge and discharge such that a capacitance associated with the first conductor may be determined that is based on the drain currents.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: February 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Michael J. McNutt, Robin C. Sarma, Yu-Sang Lin
  • Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies
    Patent number: 6856000
    Abstract: An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: February 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Joe R. Trogolo, William Loftin, William F. Kyser, Jr.
  • Method of forming integrated circuit contacts
    Patent number: 6833300
    Abstract: Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: December 21, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Leland S. Swanson, Gregory E. Howard
  • Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions
    Patent number: 6830980
    Abstract: Semiconductor device fabrication methods are provided in which a carbon-containing region is formed in a wafer to inhibit diffusion of dopants during fabrication. Front-end thermal processing operations, such as oxidation and/or anneal processes, are performed at high temperatures for short durations in order to mitigate out-diffusion of carbon from the carbon-containing region, such that carbon remains to inhibit or mitigate dopant diffusion.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: December 14, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Majid Movahed Mansoori, Donald S. Miles, Srinivasan Chakravarthi, P R Chidambaram
  • Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (“ESD”) protection
    Patent number: 6831337
    Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: December 14, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiqiang Wu, David B. Scott
  • Multistage deposition that incorporates nitrogen via an intermediate step
    Patent number: 6828200
    Abstract: The present invention forms a nitrided dielectric layer without substantial harm to a semiconductor layer on which the dielectric layer is formed. The invention employs a multi-stage process in which dielectric sub-layers are individually nitrided before formation of a next dielectric sub-layer. The net result is a nitrided multi-layered dielectric layer comprised of a plurality of dielectric sub-layers wherein the sub-layers have been individually deposited and incorporated with nitrogen.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: December 7, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Mark Visokay, Luigi Colombo
  • Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer
    Patent number: 6815801
    Abstract: The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 located over a first epitaxial layer 130, wherein the second epitaxial layer includes at least two dopant profiles 143, 147. The vertical bipolar transistor 110 may further include a collector 154, a base 156 and an emitter 158 located over or within the second epitaxial layer 140.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: November 9, 2004
    Assignee: Texas Instrument Incorporated
    Inventors: Gregory G. Romas, Darrel C. Oglesby, Jr., Scott F. Jasper, Philip Najfus, Venkatesh Govindaraju, ChunLiang Yeh, James Lisenby