Abstract: The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential is applied to the semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode will be partially or wholly formed with copper. Both the anode and the semiconductor will be exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolytes solution below 25° C. the rate of self annealing grain growth will increase reducing the final resistively of the copper lines.

Abstract: The present invention discloses a polishing pad that can facilitate process stability, extend length of use, and mitigate process non-uniformity and process induced defects for chemical mechanical planarization processes. The polishing pad of the present invention is a composite of a top pad and a sealed sub-pad. The sealed sub-pad has a sealing mechanism that mitigates liquid penetration into the sub-pad thereby maintaining a substantially uniform compressibility of the sub-pad and the polishing pad and extending a useable life of the polishing pad.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: Correcting a mask pattern includes accessing a record associated with an uncorrected pattern that comprises segments. The record associates each segment with a correction grid of a number of correction grids, where each correction grid comprises points. A segment is selected, and an optimal correction for the segment is determined. A correction grid associated with the segment is determined. The segment is snapped to a subset of points of the associated correction grid, where the subset of points is proximate to the optimal correction, to form a corrected pattern of a mask pattern.

Abstract: A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielectric layer (45) during the hardmask (65) etch process.

Abstract: A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate.

Abstract: A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.

Abstract: A semiconductor device (200) that includes a semiconductor substrate (210), semiconductor features (230, 235, 240, 260) located thereover and an insulating photoconductive layer (270) coupling the semiconductor features (230, 235, 240, 260). The photoconductive layer (270) is configured to provide conductivity between the semiconductor features (230, 235, 240, 260) in a presence of a plasma.

Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.

Abstract: A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well (220). The semiconductor substrate (210) is doped with a first type dopant, and the well (220) is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device (200) also comprises first and second electrodes (310, 320), wherein at least the first electrodes (310) are located over the well (220) and first dielectric (250). A second dielectric (510) may be located between the first and second electrodes (310, 320).

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110), (140) act to suppress the stress created in the terminated metal lines (100), (130) during thermal cycling.

Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.

Abstract: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.

Abstract: A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C.

Abstract: A multiple image photolithography system includes a radiation source (18) projecting electromagnetic radiation along a path. A reticle cartridge (26) is located in the path of the projected radiation. The cartridge (26) includes a photomask (34,36) located in the path of the projected radiation and a Fabry-Perot interferometer (54) located in the path of the projected radiation. A radiation-sensitive material (30) is located in the path of the projected radiation such that the projected radiation encounters the reticle cartridge (26) before the projected radiation encounters the radiation-sensitive material (30).

Abstract: The present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer (114) on top of a native oxide layer above a silicide layer (110) of the semiconductor wafer and then reducing the native oxide layer to form low resistance contacts. The native oxide layer is reduced using a rapid thermal annealing process within a temperature range to preserve the integrity of the silicide layer (110) and reduce excess silicon consumption. The temperature range can be greater than 350° C. and less than 615° C., but is optimal between 485° C. to 550° C.

Abstract: The present invention provides a system for reducing power consumption in a memory device containing a memory array having a number of memory cells. The present invention raises a supply voltage of a row of memory cells from a first voltage to a second voltage whenever the row of memory cells is selected for access (102) and lowers the supply voltage of the row of selected memory cells from the second voltage to the first voltage after the row of selected memory cells has been accessed (106). The first voltage is low enough to reduce power consumption of the memory device, but is high enough to retain data stored in the memory device. The second voltage is a nominal operating voltage sufficient to access the row of selected memory cells while maintaining the performance and stability of the row of selected memory cells.

Abstract: According to one embodiment of the invention, a method for manufacturing a bipolar junction transistor includes implanting a first base dopant in a semiconductor substrate, forming an epitaxial layer outwardly from the semiconductor substrate, and forming a dielectric layer outwardly from the epitaxial layer. The method also includes etching a first portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and implanting an emitter dopant in the emitter polysilicon layer. The method further includes etching a portion of the emitter polysilicon layer and a second portion of the dielectric layer to form an emitter polysilicon region having sidewalls, forming nitride regions on the sidewalls, and implanting a second base dopant in the semiconductor substrate. After implanting the second base dopant, an annealing process is performed for the semiconductor substrate to form an emitter and a base.