Abstract: Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and complement input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or complement input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An inverter tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output.

Abstract: Scan testing of complex electronic logic circuits for the detection of AC delay faults is improved without the addition of dummy or test-only latches by connecting the shift register latches according to the order determined by the method of first listing all shift register latches in the scan chain with all the combinational circuit outputs traceable from the output; sorting this list in the order of number of outputs controlled, i.e., touched in the forward trace; listing each unique combinational circuit output; sequentially assigning the order of the SRLs in the scan chain so that adjacent SRLs do not control any of the same circuit outputs; when this is not possible assign adjacent SRLs so that the fewest common circuit outputs are controlled by adjacent SRLs or if any remain unassigned, insert an output SRL between adjacent SRLs. The additional consideration of physical distance between SRLs may be added as an ordering criterion.

Abstract: A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.

Abstract: A SRCMOS sense amplifier is provided with a latch in the output stage. When a sense amplifier input signal propagates through the circuit and reaches the output stage, a reset signal is generated resetting and charging the input stage and an enable buffer stage of the amplifier to allow the input stage to begin receiving new data while previous data is latched in the output stage. An output stage reset enable is generated when data is at the output terminals of the output stage. The reset enable is combined with a clock signal in a separate output stage reset circuit to reset the circuit on a clocked basis. A further input to the output stage reset circuit is a feedback from a next circuit stage indicating that the data has been properly received in the next stage. The output stage may be reset either in response to the feedback signal from the next stage or in the presence of the reset enable and the clock signal.

Abstract: A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

Abstract: A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.

Abstract: A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string.

Abstract: In a pipeline processor, the identities of the highest and lowest numbered registers of a subset of general registers affected by a load multiple register (LMR) instruction are stored. The number of the lowest numbered registered of the subset is incremented as the registers are loaded. In the event that a next sequential instruction requires the contents of one of the registers in the subset, the number of the required register is compared with the incremented number and the decoding phase of the next instruction is allowed to proceed when the required register has been loaded as indicated by the incremented number. The identity of the highest numbered and the next to highest numbered registers loaded by the LMR instruction are recorded in a target register and an exclusive or-circuit is provided to determine whether the total number of registers loaded by the LMR instruction is an even number or an odd number.

Abstract: A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register.

Abstract: In a multiprocessor system, a plurality of data processors are each equipped with a local, level 1, cache and have access to a main memory through memory access circuit having a level 2 cache and a single register arbiter. The single register includes a primary queue defining priority of requests from the plurality of processors and a secondary queue defining processor requiring access to main memory. The register contains one position for each of the processors served and employs a pointer for demarcation between the primary and secondary queues. When a request is detected, the highest priority processor in the primary queue is served and when the requested memory address is in the level 2 cache, it will be retrieved and the identity of the served processor will be moved to the low end of the primary queue as defined by the pointer.

Abstract: A computer connected to an ISDN central office switch via an ISDN digital subscriber line, provides management information regarding activities of a plurality of telephone agents. The computer has shared call appearances with a number of telephone agent stations and receives shared call appearance associated messages from the switch reflecting call handling messages exchanged between the ISDN and each of the agent stations. The messages are interpreted by the computer, which generates station status information and management information such as the number of calls handled, average holding time per call, etc. The computer may be connected simultaneously to several central offices via ISDN subscriber lines and generate management information for a group of geographically separated agents, such as home telemarketing agents operating out of their individual homes and connected to different central offices.

Abstract: A computer connected to an ISDN switch via an ISDN digital subscriber line, has shared cell appearances with a number of telephone stations connected to the switch and on the basis of shared call appearance associated messages from the switch, controls the forwarding of calls directed to the stations with which it has a shared call appearance. The associated messages are interpreted by the computer, which generates station status information. The computer responds to messages associated with predefined ones of the stations to select an alternate destination for the call and to transmit ISDN messages to the switch to cause the call to be forwarded to the selected alternate destination. Calls may be forwarded depending on call type, called number or other criteria. The computer responds to calls forwarded to it in the event that an associated station is busy and connects a holding party to the principal phone when the principal phone is no longer busy.

Abstract: Two separate switching systems, a first one for switching packet oriented data and a second one for switching circuit oriented data as known from the state of the art can, according to the invention and with regard to their function, be integrated into a single switching system. This is realized by storing the packet oriented data in a first section of a switch memory (33) and the circuit oriented data in a second section of this same switch memory (33).With this realization additional advantages occur such as a movable boundary in the switch memory (33) between the packet oriented section and the circuit oriented section and a saturation monitoring that can be realized in a simple fashion in the switch memory (33).

Abstract: A switch system for circuit and/or packet-switched communications comprising a central controller; a clock signal source; a pair of serial memories and a series of consecutive access units each of which being linked on the one hand with an associated subscriber terminal and on the other with the read and write terminal of an associated memory location of the first as well as the second serial memory, the input and the output of the two serial memories being linked with the central controller and the information stored at the memory locations of the first and the second serial memories permitting to be transferred from the first to the last access unit and from the last to the first access unit, respectively, under control of the clock signals, the central controller generating consecutive patterns with always an equal number of time slots, each containing a predetermined number of clock signal periods in which at least an amount of information bits, each having a first or a second binary value, can be written

Abstract: The invention relates to a switching module for asynchronous time multiplex comprising at least one junction switch for transmitting packet-switched information from one bus (14) to another bus (16). The junction switch comprises a translation memory (9) for translating packet addresses into new addresses, a comparator (10) for selecting the packets that are to be routed to another bus, a queue memory (12) for storing selected packets until an insertion circuit places the selected packets into the queue memory (12) on the other bus (16). With the aid of a such junction switch, a flexible network structure can be realized, the traffic of packets on the different buses can be mutually asynchronous and virtual circuits can be realized with the aid of the translation memory (9).

Abstract: A voltage controlled oscillator (VCO) comprises the series arrangement of two signal inverters whose outputs are coupled to the input of the first signal inverter through a feedback loop, and a control circuit including a series arrangement of two diodes arranged in the same direction, whose interconnected electrodes are coupled to the input of the first inverter. The other electrodes of the diodes form inputs for two control voltages with which the frequency of the VCO can be varied over a continuous range. The VCO is used in a phase locked loop which includes a phase detector for generating an error signal representative of a phase difference between a reference signal and a signal taken from the VCO, and a loop filter for producing a control signal from the error signal. The phase detector is arranged as an EXOR gate with a first input for the reference signal voltage and a second input for the output voltage of the VCO.

Abstract: A transceiver arrangement for full-duplex data transmission over a two-wire circuit (6) comprises a transmitter part (1-4), a receiver part (7, 8, 11-15), a hybrid junction (5) to interconnect the transmitter and receiver parts and the two-wire circuit (6), and an echo canceller 9 whose input is connected to the transmitter part and whose output is connected to the receiver part, the arrangement further comprising switching means (S.sub.1) enabled in a test mode for disconnecting the receiver part (7, 8, 11-15) from the two-wire circuit (6). With a single test the proper functioning of the transmitter and receiver parts of the arrangement as well as that of the echo canceller (9) can be checked, because the arrangement also comprises switching means (S.sub.

Abstract: The connector comprises two conector portions (1, 3), each of which comprises an inner contact member (5, 49) which is coaxially surrounded by an outer contact member (23, 59) whereto it is mechanically connected via an insulating body (9, 53). At its free end each contact member (5, 23, 49, 59) comprises a contact face (5', 23', 49', 59') which extends perpendicularly to its axis, at least one (5', 59') of each pair of cooperating contact faces (5', 23'; 49', 59') being so large that, after the coupling of the two connector portions (1, 3), a suitable electrical connection is realized between the cooperating contact members (5, 23; 49, 59) it the axes of the two connector portions have been displaced with respect to one another no more than a predetermined distance (d).

Abstract: A control amplifier enabling large bandwidths (.apprxeq.2 GHz) and a large dynamic control range (.apprxeq.25 dB). The amplifying element is a MESFET. This MESFET is automatically biased. Thus, FET's whose pinch-off voltage is subject to a large variation can be used without further adjustments.

Abstract: Personalized telephone features are made available to subscribers away from their home base. A nationally accessible data base system stores feature data in association with personal identification numbers. A subscriber wishing to use personalized features while away from the home base dials a special code from a station connected to any exchange which has access to the data base and presents the personal identification number. The corresponding feature data is retrieved from the data base and stored in the exchange in association with the station from which the request was initiated and telephone service will be rendered in that exchange with the subscriber's personalized telephone features. A temporary office arrangement may be established in which the personalized features will be immediately available on incoming and outgoing calls for a period of time specified by the subscriber. In one embodiment the feature data is stored on a credit card and transmitted to the exchange by a card reader.