Abstract: In a processor system having a central processor and secondary support processor mounted on a backplane board, a separate peripheral interrupt bus is provided for each secondary support processor to give full interrupt priority capability to peripheral devices connected to the support processors. The support processors (110, 120) and certain of the system's peripheral interface circuits (102, 104) are connected to the system's central processor (101) via a primary interrupt bus (105) and other peripheral interface circuits (112, 114, 122) are connected to their associated secondary processors (110, 120) via separate interrupt buses (115, 125) all on the same backplane board. The backplane board is divided into an upper section and a lower section and the primary interrupt bus and the interrupt request and acknowledge terminal pins for all circuit boards are in the lower section.

Abstract: A work desk has an adjustable height working surface that is raised by a force applied by a lockable gas spring via a first pulley system. The first pulley system doubles the travel of the working surface as compared with the travel of the piston of the gas spring. A second pulley system ensures that all parts of the working surface are raised by an equal amount. Four slides guide the movement of the working surface. The combination of the slides and second pulley system allows the working surface to be closely held with a minimum of lateral or vertical play when the gas spring is locked. The first pulley system, in conjunction with a commercially available gas spring, the travel of whose piston is limited to 71/2 inches (190 mm), permits a vertical travel of 15 inches (380 mm) for the working surface. This travel is adequate to permit a broad range of operators to use the work desk while working in either a sitting or a standing position.

Abstract: A pair of connectors (10 and 11) having insulation piercing terminations or contacts (14, 15, 16 and 17) arrayed in columns and rows and strain relief grooves (18 and 19) associated with designated terminations in each column are stepped relative to a pair of wire cutting and stuffing devices (58 and 59) to present successive columns of terminations to receive wires. Following the presentation of each pair of columns of terminations, the wire cutting and stuffing devices are shifted by cam track devices (85, 86, 136 and 137) to position the cutting and stuffing devices to insert wires in the terminations in the designated rows of terminations. As the cutting and stuffing devices are shifted, wire guides (108 and 109) are positioned to lay the wires in designated strain relief grooves associated with the respective terminations. Each wire is cut by the wire cutting device at a point closely adjacent to the termination receiving a wire.

Abstract: A method and arrangement for scheduling the transmission of data files among a plurality of interconnected computers is disclosed. When a first computer desires to transmit data files to a second computer, the first sends a short duration message to the second defining a future time when transmission will occur. If this future time is available on the second computer, a short duration acknowledgment message is returned to the first. If the future time is not available on the second computer, no acknowledgment message is returned. The first computer transmits the data files to the second at the future time, if an acknowledgment message has been received. Such data file transmission does not occur if no acknowledgment message has been received. However, the first computer may send a new request specifying a different future time. Alternatively, a request message may contain a plurality of future times for data file transmission.

Abstract: An adjustable incremental load simulator 200 acts upon a telephone control processor 300 to drive the processor toward and into an overload state. This is accomplished by reducing the number of processing cycles available for system task execution by execution control 360. The simulator 200 pulses an interrupt circuit 350, thereby halting the execution of system tasks for a fixed number of processing cycles. The adjustable incremental load simulator has an adjustment which controls the rate of generation of interrupt signals and thereby controls the rate at which system task execution cycles are made unavailable to the execution control. The performance of the system is monitored via a display 150; thus, the simulated incremental load can be adjusted while system performance is monitored.

Abstract: A connector 14 with rows of contacts 12 is placed in a holder carriage 22 which is loaded into a wire insertion tool 10. Insertion blades 56 and 57 are moved by a trigger mechanism 17 to insert a pair of wires 11 into two contacts whereupon the blades act to sever excess sections of the wires at points closely adjacent to the contacts. Upon release of the trigger 17, an index mechanism 23 is operated to move the holder carriage 22 and the connector to position the next two contacts in alignment with the insertion blades 56 and 57.

Abstract: Apparatus for mounting a movable superstructure on a fixed base is disclosed. The superstructure, a video display unit, is attached to a cylindrical segment journal which rests on a matching cylindrical segment socket. The journal rotates within the socket as the video display unit is tilted back and forth. Two helical springs are each attached to the superstructure and the base in such a way as to counteract gravitational forces and to tend to restore the superstructure to a neutral tilt angle when it is moved therefrom. The surfaces of the journal and socket have enough friction to exceed the relatively small differences between the gravitational forces tending to move the superstructure further from the neutral tilt angle and the spring forces tending to restore the superstructure thereto. As a result, the superstructure will maintain any position but can be moved (tilted) by overcoming only the relatively small frictional force. In one constructed model, a video display unit superstructure weighing 27.

Abstract: An arrangement for serving an operator assistance request detected in a first operator assistance system from an operator position in a second operator assistance system. If a first operator assistance system is overloaded or has no attended operator positions, the two operator assistance systems cooperate to establish a connection between the customer requesting operator assistance and the operator position in the second system. The attending operator at that position keys information into the operator position for transmission to the first system. Responsive to this data, the first system enters data, such as billing data, into its records, and sets up connections, such as a connection for a person-to-person call, in its switching network. The arrangement can be used to transfer operator assistance requests at night, during overload, or to specialized operators not available at the first office.

Abstract: A method and apparatus for controlling a cellular mobile telecommunication system. A switch and a telecommunication control complex cooperate to set up connection between a telecommunication network, such as the common carrier public telephone network, and a plurality of mobile units. The switch sets up connections between trunks to the telephone network and communication links connected to the cell sites of the mobile telecommunication system. The telecommunication control complex, including a mobile telecommunication controller and the cell site controllers, controls the radio connections between these communication links and the mobile units.

Abstract: A method of generating the digital representation of a sine wave. A digital signal processor is used to generate the sample digital values, spaced at period T, of a sine wave of frequency F, using the value of the previous sample, e, the corresponding value of cosine, f, and two constants, c=sin2.pi.FT and d=cos2.pi.FT. The next value of sine, S=ed+cf; the value of the corresponding cosine, C=df-ce. The magnitude of c and d are rounded up so that c.sup.2 +d.sup.2 .gtoreq.1. Any calculated values of S or C which exceed unity in magnitude are limited to a magnitude of unity. This limiting operation accomplishes the normalization operation necessary to avoid exponential build-up due to accumulated round-off errors, and does so more efficiently than was previously possible. Sine waves with a 50 dB signal to noise ratio have been generated using this method.

Abstract: An arrangement for generating an encryption key for use in encrypting communications between a mobile radio telephone unit and a base station is disclosed which can be readily changeable in real time. Each mobile unit is equipped with a machine-readable nonbroadcast code and the base station can access a translation table correlating the nonbroadcast code with the public directory number of the mobile unit. Upon changing frequencies, as for example, when a mobile unit moves from one geographical cell area to another, the current and previous frequencies or channel numbers are left to select sets of digit positions in the nonbroadcast code. The contents of these digit positions are then convolved and inserted into a modified version of the nonbroadcast code generated by convolving the original code with a shifted replica thereof. The key so generated may be used to encrypt communications for the use of any known encrypting circuitry.

Abstract: A system for efficiently switching time multiplexed digital signals of different bit rates. A switch is described including switch modules each of which can switch data and/or voice 56 kilobit/second (kb) full-rate channels and 2.4 kb, 4.8 kb, and 9.6 kb subrate channels. All signals from incoming channels are stored in a signal memory and are transmitted to outgoing channels under the control of addresses stored in a control memory. The frame offset of each channel with respect to a standard superframe is detected and used to calculate the addresses to be stored in the control memory. Various arrangements are shown to minimize high speed signal and control memory requirements, and to simplify the process of generating control memory contents.

Abstract: A data communication arrangement in which an interface processor effects the transmission of messages between two processors of a multiprocessor system. The interface processor is connected to the communicating processors via direct memory access circuits. A sending processor stores messages in a send buffer in memory of the sending processor and controls a pointer in that memory indicating the loading of message into that buffer. The interface processor reads this pointer and the messages, and writes a pointer and the messages in a receive buffer of a receiving processor. The interface processor limits the loading of new messages into the send buffer by delaying the updating of an unload pointer, creating memory space for new messages, until the receiving processor has processed the transmitted messages. Messages can also be used to initiate the transfer of a block of data from the memory of one processor to that of another.

Abstract: A multiprocessor arrangement in which the individual program functions of a program process are executed on different processors. Data shared by different program functions is stored in shared memory and the programs are stored in local memory of the individual processors. One processor calls for the execution of a program function by another processor by causing the program address and a pointer to the program function context to be loaded into a work queue of the called processor. Input/output modules are treated as processors. Facilities are provided for the transfer of blocks of data over the interconnection bus system. Virtual address are translated to physical addresses in one facility common to all processors.

Abstract: A cable supporting clamp (10) for the orderly routing of flat electrical cables (28, 29, 30) at the interconnection side of electrical equipment frames. A pair of jaws each formed of a pair of arms (18-19; 20-21) extending from one side of a backplate (15) define slots (22, 23) adapted to receive the cable or cables. The cables are trapped in the slots by a pair of nubs (24-25; 26-27) at each jaw extending inwardly into the slots at the ends of the jaw arms (18-19; 20-21). Bracket means (31, 35) are provided at the other side of the backplate (15) for slidably mounting the clamp (10) on a frame cross-member (11).

Abstract: A circuit for the detection of errors in single and double word arithmetic logic unit operations.A microprogram processor achieves self-checking of arithmetic logic unit functions by performing single-word operations in the duplex mode and double-word operations in the simplex mode. The double-word operation is checked by performing the operation twice, generating a parity bit for each output word and comparing the parity bits generated for the two operations.

Abstract: A detection circuit for detecting a mismatch between the output signals of duplicated logic units (10a, 10b). The output terminals of one of the duplicated logic units are correspondingly connected to the output terminals of the other duplicated logic unit, while the power supply leads of the duplicated logic units (10a, 10b) are connected to a positive voltage source (32) through a current imbalance detector. Any mismatch between the output signals of the duplicated logic units (10a, 10b) will result in the detection of a large imbalance of current being supplied to the duplicated logic units (10a, 10b). Upon detection, the detector will generate an error signal.

Abstract: An arrangement for controlling switch connections (115) between a plurality of accessing circuits (113a through 113n) and a plurality of peripheral circuits (116) prevents simultaneous connections by more than one accessing circuit to any one peripheral circuit. Address signals which identify requested connections are decoded to generate connection request signals. A resistor network (501A through 501N and 506A through 506N) responsive to the connection request signals generates voltage level signals representative of the number of accessing circuits requesting connection to each peripheral circuit. The voltage level signals are compared to a threshold signal to generate a connection enable signal if only one accessing signal is requesting connection to a given peripheral circuit and to generate a busy signal if more than one accessing circuit is requesting connection to a given peripheral circuit. Switch connections are completed only after receiving a connection enable signal.