Abstract: A zero insertion force connector for making contact with the electrical terminals of four printed wiring boards. Two pairs of parallel plates (16, 17; 18, 19), each pair mounted for lateral movement and having a plurality of terminals (29) for making contact with the corresponding electrical terminals of two printed wiring boards when inserted therebetween, are each separated and closed by the rotation of a shaft (37) having two cam plates (39, 40) mounted near the opposite ends thereof. The two cam plates (39, 40) mounted next to the opposite ends of the two pairs of plates (16, 17; 18, 19), respectively, converts the rotational movement of the shaft (37) to the lateral movement of the two pairs of plates (16, 17; 18, 19) thereby separating and closing each pair of plates (16, 17; 18, 19).

Abstract: A circuit for the detection of write errors in a memory with selectable byte addressing. The memory is capable of selectively writing bytes within a memory word by decoding control signals and address signals received from a processor. The decoder and transmission path of the control signals are checked by the processor generating incorrect parity for the bytes which are not to be written. The memory decodes the control signals, checks the parity of the bytes, and generates a write parity error if the decoder selects a byte with incorrect parity to be written. If the memory malfunctions and spuriously writes an unselected byte, this fact will be detected when the unselected byte is read. The memory checks each byte read for parity, and incorrect parity causes the memory to transmit a read memory error to the processor.

Abstract: An impedance/admittance measuring circuit generates an output signal which is representative of the real or imaginary part of the impedance or admittance of a connected load. An excitation signal comprising a square wave having a fixed magnitude is generated and applied to a load. The response signal resulting from the excitation signal is filtered by a two pole bandpass filter (106). The filter output signal is used to control the excitation signal generator (101, 102) such that an oscillatory feedback loop is formed. By controlling the load connection and the phase relations between the excitation signal and the filter output signal, the magnitude of the output signal is representative of the real or imaginary part of the impedance or admittance of the connected load (103).

Abstract: A message storage system (104) deletes trailing silence from messages stored therein. Voice messages are converted to digital signals and stored as data blocks in a digital storage system (114a). Voice signals are detected in messages to be stored and voice present bits are generated and included in the individual data blocks to indicate whether voice signals are present in the data blocks. During storage of the data blocks, the voice present bits which identify data blocks containing no voice signals increment a counter (311), and voice present bits which identify data blocks containing voice signals clear the counter (311). The final count in the counter is representative of the trailing data blocks which do not contain voice signals, i.e., silence, and these data blocks are deleted from the digital storage system.

Abstract: A plurality of stored-program controllable computer units MP.sub.(o) -MP.sub.(n) are associated with a somewhat greater number of program stores PS.sub.(o) -PS.sub.(N+1) in an arrangement with a main memory unit MBM and an activity memory unit AM in a manner such that each computer unit is only assigned to use that program store which has already been loaded with a program paged from the main memory unit. When a computer unit finishes with the program store it had been using, it obtains a new, already-loaded program store with which to work and causes the main memory unit to reload the store with which it has just finished working with a new program. In this manner, no computer unit must wait while a program is being paged into any program store.

Abstract: A trunk test circuit (107) is disclosed in a stored program controlled toll switching system (103) for executing tests to determine transmission quality of communication trunks connected to a remote telephone office (101). A detector circuit (200) has a novel feedback arrangement comprising a selectable frequency source, comparison circuitry, and a sample and hold circuit, for generating output test signals corresponding to priorly received incoming test signals. The detector circuit is responsive to control signals received from a sequence control circuit (201) for receiving, measuring, and transmitting test signals on a communication trunk (102) under test.

Abstract: A message storage system (104) deletes leading silence from messages to be stored therein. Voice messages are converted to digital signals and stored as data blocks in a digital memory (601). Voice signals are detected in messages to be stored and a voice present signal is generated during periods of time when voice signals are detected. The memory is set to a starting location after the storage of each group of four data blocks of a message until a voice present signal is generated, thereby deleting leading data blocks which do not contain voice signals.

Abstract: A trunk interface circuit (105) is disclosed for executing communication and signaling functions associated with telephone calls between subscriber stations of separate telecommunication systems (100, 140). A semiautonomous control circuit (200) is responsive to state signals generated from a central control circuit (120) for establishing the trunk interface circuit (105) in a plurality of states. The semiautonomous control circuit (200) comprises a memory (320) having predetermined data stored therein corresponding to each of the plurality of states. A processor (300) within the semiautonomous control circuit (200) executes certain of the communication and signaling functions as determined by the stored data corresponding to the present state of the trunk interface circuit (105). The communication functions comprise reception of periodic charging pulses from a distant office and subsequent transmittal of signals to the central control circuit (120) representative of the charging pulses.

Abstract: An arrangement tears down existing connection paths in a two stage switching network wherein switching paths are set up progressively by control circuits in both switching stages. A first-stage setup command is received by a first-stage control circuit and the second-stage control circuit of the previously established connection path. The first-stage control circuit responds to the first-stage setup command to set up a connection path through the first-stage switch and the second-stage control circuit responds to the first-stage setup command to tear down the previously established connection path.

Abstract: An electronic loop identification circuit identifies loaded and nonloaded customer telephone loops. The loops can then be segregated to allow separate balance networks to be used for hybrid circuits which connect the customer loops to a digital switching office. Separate balance networks for loaded and nonloaded loops improve singing margin on those loops. An impedance measuring circuit (214) measures the real part of the impedance of a connected loop which is compared to a reference signal. If the real part of the loop impedance is greater than the reference signal, a loaded loop is identified; and, if the real part of the loop impedance is less than the reference signal, a nonloaded loop is identified. The circuit includes a self-calibrating arrangement which connects a reference impedance (209) to the impedance measuring circuit so that a capacitor (304) held reference signal can be set before each loop identification operation.

Abstract: A phase locked loop circuit (100) for generating a periodic clock signal from a controlled oscillator circuit (130) in phase coincidence with a synchronous aperiodic data input signal is disclosed. A pulse of the data signal and a corresponding pulse of the clock signal are applied to a bistable circuit (FF1) having an output signal indicating which of the pulses occurs first in time. The pulses are further applied through delay circuitry (DLY1, DLY2) to another bistable circuit (FF2) having an output signal indicative of the magnitude of phase difference between the pulses. The output signals of the bistable circuits (FF1, FF2) are applied to a multilevel driver circuit (140) which generates an error correction signal pulse defining magnitude and direction of a correction signal to be applied to the oscillator circuit (130).

Abstract: A message storage system (104) cooperates with a plurality of telephone switching offices (102, 122) to provide a variety of voice storage services to subscribing customers served by the switching offices. Control signals and voice messages are delivered to the message storage system in analog form and converted to digital signals. A processor circuit (111)interprets the control signals and sends work lists to a plurality of microprocessor controlled message controllers (113a through 113n) which in turn each control a plurality of disc transports (114a through 114n), a time multiplex switch (115), and a larger plurality of buffer circuits (116) wherein the messages in digital signal form are speed buffered for storage in the disc transports. The message controllers control the flow of digital data words between the buffer circuits and the disc transports via the time multiplex switch to provide highly efficient mass storage and retrieval of messages.

Abstract: A data processing system includes a memory arrangement comprising a main memory, and a cache memory including a validity bit per storage location to indicate the validity of data stored therein. Cache performance is improved by a special read operation to eliminate storage of data otherwise purged by a replacement scheme. A special read removes cache data after it is read and does not write data read from the main memory into the cache. Additional operations include: normal read, where data is read from the cache memory if available, or, from main memory and written into cache; normal write, where data is written into main memory and the cache is interrogated, in the event of a hit, the data is either updated or effectively removed from the cache by invalidating its associated validity bit; and special write, where data is written both into main memory and the cache.

Abstract: A conference circuit (150) is disclosed for use in a telephone switching system (100) to provide communication among three or more subscriber stations (101, 102, 103). The subscriber stations (101, 102, 103) are connected to a plurality of ports (P0, P1, P2) of the conference circuit via communication lines (104, 105, 106) and a switching network (130). Amplification circuitry (210, 211, 212) connected to the ports (P0, P1, P2) provides input signal amplification to assure adequate transmission quality. A sensing circuit (220, 221) detects signals generated by subscriber station transitions and generates timed control signals to adjust the magnitude of amplification of input signals from the subscriber stations (101, 102, 103) for a predetermined period of time. Circuits (S1, S2) which supervise the states of junctor circuits (121, 122) connected to the conference circuit (150) provide for further gain control of the amplification circuitry (210, 211, 212).

Abstract: A fault detection arrangement for a data rate conversion system is disclosed. In accordance with the embodiment one forty-bit digital word representing a speech segment is transmitted from a digital word source to a first-in, first-out (FIFO) buffer every 1.28 milliseconds at a 1 megahertz per second bit rate. The bits are read from the FIFO at a 31.25 kilobit per second rate and applied to a digital-to-analog converter. The FIFO contains at least thirty-nine bit storage positions and by design no bit is read from the FIFO until a predetermined period of time after a first bit has been written therein. FIFO empty fault signals are generated if the FIFO ever becomes empty and FIFO fault signals are generated if the FIFO ever becomes full.

Abstract: The disclosed analog to digital converter employs a single signal propagation path thereby necessitating only one holding capacitor (101) per stage (STAGE 1) of coding. The first terminal (B) of each holding capacitor (101) is connected to a reference voltage (L1) such as a resistive divider (106, 116, 126, 136, 146, 150, 151, V.sub.HI) which has binary weighted taps (L1-L5). The other terminal (A) of each holding capacitor (101) is connected to the analog signal input (INPUT). The reference voltage (L1) and the analog sample (V1) are compared and, for a zero decision, the stored analog sample (V1) is directly passed on to the subsequent stage (STAGE 2) by a buffer circuit (102). For a one decision, the aforementioned first terminal (B) of the holding capacitor (101) is switched from the tap of the resistive divider to circuit ground thereby subtracting that binary weight (L1) from the signal (V1) stored on the holding capacitor (101).

Abstract: A novel pulse detection circuit for recognizing undesirable noise pulses within digital logic circuitry is disclosed. The detection circuit allows for pulse amplitude and pulse width discrimination and will generate output signals indicative of the presence of pulses of amplitude greater than a selected amplitude and width less than a selected duration. Logic voltage comparators and a variable reference voltage source are used to allow for variable pulse amplitude discrimination of both positive transition and negative transition incoming signals. An incoming signal of greater amplitude than a reference signal will be reflected in both a direct output pulse signal and an inverted output pulse signal of the voltage comparators. The direct output pulse signal is applied to a first flip-flop after being delayed by a first given interval of time.

Abstract: Time-slot interchange circuitry for use in a time-division switching system is disclosed having n+1 input interface units and n+1 output interface units to serve n PCM lines. One of each group of n+1 interface units is designated a spare unit and control circuitry is disclosed for autonomously channeling incoming data words or outgoing data words through a spare unit and for autonomously altering the control for the spare unit in the event of failure of a unit in service.

Abstract: A clock pulse circuit is disclosed in which two clock pulse generators operate in an active-standby circuit arrangement to provide a highly reliable single clock output signal comprising a sequence of repetitive pulses. The arrangement comprises a plurality of counters to count pulses generated by each of the clock pulse generators. Comparison circuitry connected to the counters generates an inequality signal indicative of an apparent failure of one of the generators. Logic circuitry responsive to the inequality signal will cause subsequent clock output pulses to be derived from the operating pulse generator. In one embodiment of this invention an actual failure is distinguished from an allowable phase drift of the generator output signal. Another embodiment utilizes additional counters responsive to complementary generator output signals to maintain an uninterrupted sequence of clock output pulses regardless of a failure in either pulse generator.

Abstract: A DC to DC converter is disclosed wherein the output voltage is regulated by the control of current pulses in an inverter stage. The converter output voltage and a defined reference voltage are compared to generate error signals and current flow in the inverter stage is monitored to generate proportional current signals. The error signals are directly compared to the current signals by a comparing circuit which comprises a voltage ampliflier and a current source. The error signals are coupled to the voltage amplifier which maintains a corresponding voltage on one side of a resistor. The current signals are coupled to the current source which is connected to the other side of the resistor and maintains the current flow through the resistor at a level equal to the current signals.