Abstract: An interface circuit adapted for use with a digital time division transmission system is disclosed, including a microprocessor operating in synchronism with data received over the transmission line and having a sequentially executed program, structured to service incoming and outgoing PCM lines on a periodic basis in synchronism with the bit rate of the incoming PCM bitstream.

Abstract: A time-division switching system having a space-division network with a plurality of input terminals, each uniquely associated with a first buffer memory, and a plurality of output terminals, each uniquely associated with a second buffer memory, is disclosed. Time-shared communication paths through the space-division network are predominately completed such that digital data words representing signals from both parties to a conversation are transmitted through the space-division network during the same time slot. Normally, data words representing signals from telephone subscribers are assigned to first buffer memories in accordance with a fixed distribution plan. The system includes an arrangement which modifies the fixed distribution plan when it is determined that both parties to a conversation will have their data words stored in the same first buffer memory and switches data words representing signals from the called party of the conversation to an idle storage location in a different first buffer memory.

Abstract: A bilateral solid-state crosspoint for use in a telecommunications switching network is disclosed comprising a pair of Darlington connected pairs of transistors connected in a complementary relationship. The transmission path in each direction through the crosspoint comprises a Darlington connected pair of transistors and one additional semiconductor junction. A control circuit provides base drive to the transistors to close the crosspoint.

Abstract: A table translator circuit arrangement comprises a plurality of random access word organized memories, input circuitry, output circuitry, and control circuitry. The word locations of each memory are separated into control and data locations defined by corresponding ranges of memory access addresses. Each table entry comprises one or more access control bits and associated data. Each table address defines a control location in one memory of the plurality and data locations in additional memories of the plurality. An entry to be written into the table is provided to input rotate circuitry which is controlled by a portion of the table address which defines the location at which the entry is to be written. The input rotate circuitry delivers the access control bits of the entry to a memory in which a control location is accessed and delivers the associated data bits to additional memories in which data locations are accessed.

Abstract: A test set is disclosed for measuring read/write head skew in a magnetic tape recording system. Read head skew is measured by reading a reference tape having substantially identical alternating signals recorded in all tracks thereof and measuring the time between the receipt of signal peaks of corresponding portions of the signals read from any two tracks of the reference tape. Pulses from a high frequency oscillator are counted during the time between the signal peaks to obtain counts which are representative of the read head skew. These counts are averaged over a number of cycles of the alternating signals and displayed on a digital display. Write head skew is measured by writing an alternating signal onto two tracks of a magnetic tape and reading the two tracks with a properly aligned read head.

Abstract: An arrangement for establishing communication paths through a plurality of serially connected thyristors comprising a first and last thyristor, is disclosed. Each thyristor comprises a main conduction path terminating in a first and second main conduction electrode and a control path between the first electrode and a gate electrode. The second main conduction electrode of each thyristor, except the last, is connected to the first main conduction electrode of a subsequent thyristor. To establish a path, a marking potential is applied to the first main conduction electrode of the first thyristor and gate currents, equal to or greater than the thyristor holding currents, are produced in the control paths of the thyristors in sequence and overlapped in time from the first to the last. A hold current is then produced in the second main conduction electrode of the last thyristor and the gate currents are terminated.

Abstract: A communication line interface circuit including a floating current source supplying a constant current substantially independent of loop length is disclosed. The line interface circuit is provided with circuitry for line supervision and the detection of dial pulse signaling.

Abstract: A communication line interface circuit including a floating current source supplying a constant current substantially independent of loop length is disclosed. The line interface circuit is provided with circuitry for line supervision and the detection of dial pulse signaling.

Abstract: A telephone switching arrangement is disclosed incorporating means for automatically distributing calls among a plurality of groups of call answering consoles. In the disclosed arrangement, which may be part of a telephone central office or may be located in a remote location such as a customer's premises, a directory number and a queuing register are assigned to each group of call answering consoles. Incoming calls for a particular directory number are queued in the associated queuing register and when a console of the assigned group of consoles is available, a connection is established to the available console from the line or trunk associated with a call in the queuing register. The time in queue for each call is measured and compared against upper and lower time thresholds.

Abstract: A telephone ringing circuit responds to both conventional high voltage 20Hz ringing signals and low voltage tone alerting signals. A conventional electromechanical ringer is connected across the telephone line and is responsive to high voltage 20Hz ringing signals. A high capacitance capacitor is charged by the dc voltage present on the telephone line and is discharged across the electromechanical ringer when a tone detector circuit connected across the line detects a tone alerting signal, thereby activating the electromechanical ringer.

Abstract: An automatic headlight control circuit is disclosed which will serve to turn-on automobile lights in response to pulsed external signals such as ignition pulses. A delay circuit is provided which will cause the lights to be turned-off a predetermined period of time after the external signals to the control circuit have ceased. A delay of several minutes is accomplished using an emitter follower circuit.