Abstract: A compensated driver for maintaining constant impedance during data transfer from an integrated circuit comprises an output portion having an output device to transfer data from the integrated circuit and a mimic circuit portion having a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A mimic circuit portion has a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A differential amplifier portion is adapted to generate a control voltage in response to a reference voltage and the sample voltage. A predrive portion applies either a ground or the predetermined control voltage from the differential amplifier portion to the output stage portion in response to an input, the control voltage regulating the output device in the output stage portion to achieve a more constant impedance.

Abstract: A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

Abstract: A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon.

Abstract: A phase shifting mask for use in lithographic processing of semiconductor substrates comprises a mask substrate substantially transparent to the energy beam used and a patterned phase shifting layer disposed on the mask substrate and having openings therein exposing the mask substrate. The patterned phase shifting layer is comprised of a material of differing composition than the mask substrate and is of thickness sufficient to shift the phase of an energy beam passing through the thickness of the patterned layer and the mask substrate by 180 degrees, compared to the phase of the energy beam passing through the phase shifting layer openings and the mask substrate. Preferably the phase shifting material is a siliconoxynitride and the substrate is quartz. The mask also includes a patterned layer of a material substantially opaque to the energy beam disposed on the mask substrate or the patterned phase shifting mask layer.

Abstract: A method and structure for analyzing the effect of electrical noise in an integrated circuit fabricated in a silicon-on-insulator (“SOI”) technology. The present invention uses a static noise analysis to evaluate an integrated circuit's response to electrical noise, taking into account hysteresis effect and parasitic bipolar current voltage, both of which are unique to integrated circuits fabricated in a SOI technology process. The present invention also includes a computer, computer storage device, computer program and software incorporating the method steps and simulating the testing and analysis of the circuit under test.

Abstract: A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs.

Abstract: A camshaft drive mechanism for a vee-twin engine is described. The mechanism comprises first and second camshafts which are driven by a gear on the crankshaft of an engine incorporating the mechanism. The crankshaft drive gear engages a primary (idler) gear on the first camshaft while a secondary gear on that camshaft imparts counter rotation on the second camshaft via an identical secondary gear on the latter camshaft.

Abstract: A method of configuring partitions for different circuit or other operational areas on an integrated circuit initially identifies points representing components of an integrated circuit with respect to a coordinate system having a horizontal axis and a vertical axis, and subsequently creates a first isothetic rectangular partition containing all of the identified points of the integrated circuit. The method then continues by subdividing the first isothetic rectangular partition with respect to the horizontal axis by creating a plurality of isothetic rectangular sub-partitions collectively containing all of the identified points of the integrated circuit. Each of the isothetic rectangular sub-partitions is separated by a line parallel to the horizontal axis. These isothetic rectangular sub-partitions collectively encompass a minimum area containing all of the identified points.

Abstract: A method of improving surface morphology of a semiconductor substrate when using an SOI technique comprises providing a silicon ingot positioned on a support member, orientating the silicon ingot in relation to the support member, and a cutting device, and cutting the silicon ingot along about a (100) crystal plane of the silicon ingot, preferably using a wire saw. This then provides a silicon substrate having an initial surface defining a miscut angle which is less than about 0.15 degrees from the (100) crystal plane. The method then comprises processing the silicon substrate using SIMOX processing, which includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer and annealing the silicon substrate to provide a final substrate surface. Finally, the method includes accepting the final substrate surface for further processing when the final substrate surface measures between 2-20 Å RMS using an atomic force microscopy technique.

Abstract: A method of treating the upper urinary tract of a mammal having a urethra extending to a bladder and a ureter extending from the bladder to a kidney. The method comprises initially extending a catheter system into the upper urinary tract, the catheter system having a urethral catheter infusion tube section extending through the urethra for infusion of a liquid; a urethral catheter drain tube section extending through the urethra for drainage of a liquid; a ureteral catheter tube section extending through a ureter into the kidney and having a first tube portion for infusion of a liquid connected to the urethral catheter infusion tube section, and a second tube portion for drainage of a liquid.

Abstract: A method and apparatus for providing feedback to a programmer of a web based application notifying the programmer of application errors encountered by an end user of the application. A user error table is created to log application errors when a user computer is running the web based application. The present invention searches the user error table to determine whether an application error has occurred and only those errors which occur for a first time are forwarded to a server responsible for collecting the programmer's e-mail. A server error table is created to log those error messages received by the server and only those error messages which are unique are forwarded to the programmer. The programmer does not receive duplicate error messages relating to the same error and can use the feedback provided by the present invention to correct the application in subsequent versions.

Abstract: A method of analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design. The method initially comprises providing a library of circuits for use in designing an integrated circuit chip and determining a supply current requirement and an operating voltage range for each circuit in the circuit library. The method then includes calculating an admittance matrix representing the power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid, assigning regions of the power grid to each of the ports, and placing a set of circuits from the circuit library in regions on the power grid.

Abstract: A method for laser machining parts from a strip comprises providing a strip of material from which parts are to be made, feeding the strip into a laser station having first and second lasers, and positioning the first laser with respect to the strip. With the first laser, the method then includes laser machining substantially all of an outline of a plurality of parts in sequence along the strip, leaving at least one tab portion connecting each part to the strip. The second laser is then positioned with respect to the strip and, with the second laser, the method then includes laser machining tab portions connecting parts to the strip in sequence along the strip, and separating the laser machined parts from remaining portions of the strip. Preferably, the first laser and the second laser move simultaneously in the same direction with respect to the strip during laser machining.

Abstract: A method for allocating memory in a parallel processing computing system in which there is first provided a system memory available for parallel processing and first and second threads, each of the threads representing an independent flow of control managed by a program structure and performing different program tasks. The method includes using the first thread to request memory from the system memory; allocating to the first thread a first pool of memory in excess of the request and associating the memory pool with the second thread; using the second thread to request memory from the system memory; allocating to the second thread a second pool of memory in excess of the request and associating the memory pool with the first thread; using the first thread to request further memory from the second thread; and allocating to the first thread a portion of the second pool of memory from the second thread without making a request to the system memory.

Abstract: The present invention discloses a method and apparatus for viewing and modifying the cache when accessing and processing audio file data from a server. By modifying the cache during transmission of the audio file data such that the cache is never completely depleted of the data, superior sound quality is achieved and without significant gaps in transmission.

Abstract: A voltage generator for an integrated circuit chip comprises an integrated circuit chip with a power supply having a voltage available to the chip; an inductor on or in contact with the integrated circuit chip electrically connected to the power supply through which current is driven; and a clock adapted to interrupting current flowing from the power supply through the inductor at desired time intervals to create voltage spikes above the power supply voltage. The inductor may comprise a portion of the lead frame connecting the integrated circuit chip to an integrated chip package. The voltage spikes generate a voltage about two or more times the voltage of the power supply available to the chip. Where the integrated circuit chip includes an electrical fuse and/or a battery, the fuse on the chip may be adapted to be programmed or the battery charged by the voltage spikes.

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion.

Abstract: A monitor for electrically testing energy beam dose or focus of a layer formed on a substrate by lithographic processing. The monitor comprises a substrate having in a lithographically formed layer an array of electrically conductive elements comprising a plurality of spaced, substantially parallel elements having a length and a width, with the individual elements being electrically connected, and the lengths of the elements being sensitive to dose and focus of an energy beam in lithographically forming the layer. The monitor further includes at least one pad electrically connected to the array to apply current through the array elements. Upon applying a voltage across the array elements, the suitability of dose or focus of the lithographically formed layer may be determined by the resistance of the array. Preferably, ends of the individual elements are aligned along essentially straight lines to form an array edge.

Abstract: A method of encapsulating a workpiece, particularly a microelectronic device, to achieve a very thin encapsulating layer and reduce the finished device size. The method includes positioning the workpiece in the mold cavity of a mold capable of reducing its volume while the mold compound is in a liquid state from a first volume, where mold compound may be easily added without creating voids, to a second smaller volume which defines the finished workpiece size. The second volume is below the size which would permit the void-free encapsulation of the workpiece in a conventional thermosetting plastic transfer molding machine. The mold may be opened in two stages to prevent damage to thin molded microelectronic devices by opening the perimeter of the mold first while the molded device is still being supported by large molding surfaces. The invention also includes the mold used in the method.

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer.