Abstract: The present invention is a workpiece support apparatus and method of making of using the same. A holding fixture frame supports the workpiece about the perimeter and also locates the workpiece. A series of support wires keep the workpiece from sagging inside the holding fixture frame. The support wires provide support while allowing top and bottom access to the workpiece. The workpiece remains flat at the point of the machining operation.

Abstract: The present invention provides a thermal conduction module assembly kit comprising a base being substantially planar in shape and adapted to receive on a top surface a substrate adapted to receive at least one integrated circuit having top and bottom surfaces. A cover is substantially rectangular, having top and bottom surfaces and an outer edge surface. The cover is designed to mate with the substrate such that the integrated circuit is positioned between the bottom surface of the cover and the top surface of the substrate. A removable shim member is planar in shape and has a definable vertical dimension positioned between the bottom surface of the cover and the top surface of the integrated circuit to provide a specified dimension between the top surface of the integrated circuit and the bottom surface of the cover. A positioning member has top, bottom, and inner surfaces, and is substantially circular.

Abstract: A silicon-germanium ESD element comprises a substrate of a first dopant type coupled to a first voltage terminal and a first diode-configured element. The first diode-configured element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. Preferably, the SiGe base layer ion the collector region is an epitaxial SiGe layer and the second dopant type of the emitter is diffused in to the SiGe base layer. The ESD element of the present invention may further include a second diode-configured element of the same structure as the first diode-configured element, with an isolation region in the substrate separating the first and second diode-configured elements. The first and second diode-configured elements form a diode network.

Abstract: The present invention discloses a method of controlling the precise removal of unwanted material from a light transmittable substrate for isolating and removing defects from a surface of the light transmittable substrate and for direct writing of a reticle or photomask, and the resultant reticle or photomask. The depth of ion implantation of a light absorbing material such as gallium, arsenic, boron, phosphorus, antimony or combinations thereof into the defect and/or the areas surrounding the defect on the light transmittable substrate controls the depth of material removed from the substrate. Unexpectedly, the use of laser ablation at pulses not greater than 10−5 seconds to remove the unwanted material provides precision removal while preventing heat damage to the substrate.

Abstract: A method for reducing lens aberrations sensitivity and proximity effects of alternating phase shifted masks is described. The critical features of a chip design layout are first identified. Multiple, narrow phase regions and auxiliary phase transitions, which provide additional opaque features, are then formed alongside the critical features such that a grating pattern of substantially uniform pitch is printed. Together with a complementary trim mask, the circuit pattern so delineated has reduced sensitivity to lens aberrations and proximity effects.

Abstract: A metrology apparatus for determining bias and overlay errors in a substrate formed by a lithographic process includes an aperture between the objective lens and the image plane adapted to set the effective numerical aperture of the apparatus. The aperture is adjustable to vary the effective numerical aperture of the apparatus and the aperture may be non-circular, to individually vary the effective numerical aperture of the apparatus in horizontal and vertical directions. To determine bias and overlay error there is provided a target having an array of elements on the substrate, the array comprising a plurality of spaced, substantially parallel elements having a length and a width, the sum of the width of an element and the spacing of adjacent elements defining a pitch of the elements, edges of the elements being aligned along a line forming opposite array edges, the distance between array edges comprising the array width.

Abstract: A method of encapsulating a workpiece, particularly a microelectronic device, to achieve a very thin encapsulating layer and reduce the finished device size. The method includes positioning the workpiece in the mold cavity of a mold capable of reducing its volume while the mold compound is in a liquid state from a first volume, where mold compound may be easily added without creating voids, to a second smaller volume which defines the finished workpiece size. The second volume is below the size which would permit the void-free encapsulation of the workpiece in a conventional thermosetting plastic transfer molding machine. The mold may be opened in two stages to prevent damage to thin molded microelectronic devices by opening the perimeter of the mold first while the molded device is still being supported by large molding surfaces. The invention also includes the mold used in the method.

Abstract: Electronic packages made with a high area percent coverage of blanket metal may be prone to certain kinds of ceramic defects. In aluminum nitride, these defects may be related to decomposition of the liquid sintering aid. In this experiment, unique additions to the metallization prevented the formation of certain ceramic defects. Our approach involves a unique composition used in an existing process.

Abstract: A method of making a self-aligned dynamic threshold field effect device having a dynamic threshold voltage includes depositing a mandrel layer on the surface of an SOI substrate, then etching a gate opening in the mandrel layer. The gate opening is narrowed by depositing spacer material and a highly doped region, forming a low resistance body region, is created by ion implantation. The narrowed gate opening prevents the low resistance body from connecting the source/drain regions to be formed on opposite sides of the gate-structure. A gate is formed by depositing a dielectric layer in the gate opening, and adding a layer of gate material, then chemical-mechanical polishing to the level of the mandrel layer, then removing the mandrel layer. Conventional processing is then used to create source/drain diffusion regions. The gate is connected to the body by creating a contact region at one end of the gate. The invention includes the device made by the method.

Abstract: A method and apparatus for reducing the risk of environmental contamination from mercury spillage during carry over between processing tanks during the gold ball bond removal process by providing a self-contained, compact, environmentally safe system for use with toxic chemicals and liquids. The present invention provides a self-contained, integrally molded enclosure upper and lower chambers separated by a partition. The partition has a plurality of stations integrally formed therein, each of which is capable of containing a chemical liquid. The method comprises dipping a slide containing the semiconductor chip first into a toxic liquid, then into a first decontamination station and finally into a second decontamination station.

Abstract: A process for exporting functions of a dynamic link library to an executable program on a computer provides a dynamic link library module adapted to export a plurality of desired functions, with each of the desired functions having a unique identification. The dynamic link library module includes a dispatching function adapted to recognize the unique identification each of the desired functions and export the desired function for execution by the program. There is also provided a look-up table for the executable program having therein a listing for each of the desired functions and unique identifications. The process includes loading the dynamic link library module with the program and calling the desired function by passing the desired function identification from the program to the dispatching function. Thereafter, the desired function is exported from the dynamic link library module to the program.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with hafnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper interstitial positions.

Abstract: A structure and process for joining semiconductor components. The present invention allows the flexibility of fabricating electronic components, or semiconductor chip structures, to a common point and electrically joining the different parts together at a back end level, or to a metal wiring level, to complete circuit functionality. Different combinations of front end of the line device chips may be readily joined to a common back end of the line device using a small electrical connection to form a small semiconductor chip package. Instead of packaging different groups of semiconductor chips onto different substrates and then electrically connecting each substrate together for circuit and component functionality, each group of chips can be formed on a single substrate and electrically joined on a back end wafer. These electrically connected and combined groups of chips becomes, for all practical purposes, one chip.

Abstract: A method of detecting electromagnetic radiation with an active pixel sensor photosensitive device having an extremely thin virtual pinning layer formed by inverting semiconductor material at the surface of a photosensitive region. The thin pinning layer improves blue light response. The inverted pinning layer is produced by connecting a negative potential source to a transparent conductive layer, preferably made of indium-tin-oxide positioned over most of the photosensitive region. The conductive layer is insulated from the photosensitive region by a thin insulating layer. Connection to the pinning layer is through a coupling region formed in an area not covered by the conductive and insulating layers. Red light response is improved and the depth of the photosensitive region reduced by creating a strained layer, preferably of germanium silicon, deep within the photosensitive region. The strained layer has a modified bandgap which increases the absorption rate of red light.

Abstract: A method of producing an asymmetrical semiconductor device with ion implantation techniques and semiconductor devices constructed according to this method in which a barrier of ion absorbing material of height h is positioned beside a structure on a semiconductor surface. The barrier is located at a maximum distance d from one side of the structure, and an angled ion implant is directed at the side of the structure. The maximum distance d of the barrier from the side of the structure is equal to the height of the barrier h divided by the tangent of the angle of the ion implant so that the side of the structure is shadowed from the ion implant. A second ion implant is directed to the opposite side of the structure on the semiconductor surface, thereby forming a desired implant and producing the asymmetrical semiconductor device.

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C4F8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Abstract: A method to repair Aluminum Nitride (AlN) substrates is disclosed wherein a frequency doubled Q-switched Nd:YAG laser is used to remove unwanted metallurgy. The substrate is place in a liquid filled work chamber which acts to prevent metallic species of AlN from forming. The repair site can be sealed with a novel polymer coating to prevent contamination or corrosion. Repairs can be made to buried or surface metallurgy.

Abstract: A stencil or scatterer mask for use with charged particle beam lithography such as projection electron-beam lithography comprises a membrane layer of a material having a Young's modulus of at least about 400 GPa and support struts supporting a surface of the membrane. The struts form and surrounding a plurality of discrete membrane areas of different aspect ratios aligned to design regions of an integrated circuit. The discrete membrane areas have different aspect ratios range from about 1:1 to about 12:1, and the discrete membrane areas have different size surface areas. The membrane is preferably silicon carbide, diamond, diamond-like carbon, amorphous carbon, carbon nitride or boron nitride. When used in scatterer masks, the ratio of discrete membrane area to membrane thickness is at least about 0.18 mm2/nm. When used in stencil masks, the ratio of discrete membrane area to membrane thickness is at least about 1.0 mm2/nm.

Abstract: A method of making a capacitor on a conductive surface, preferably on a polysilicon surface includes contamination cleaning the surface with a high density plasma (HDP) of a first gaseous agent, such as hydrogen, then growing a silicon nitride barrier layer on the surface using a high density plasma (HDP) of nitrogen. A layer of tantalum oxide is then deposited on the silicon nitride layer to form a capacitor dielectric layer. A second silicon nitride layer is then grown on the capacitor dielectric layer, also using an HDP nitrogen plasma with the addition of a silicon containing gas, such as silane. Finally, a conductive layer is deposited on the second silicon nitride layer to form the capacitor. The HDP plasma is heated using an inductively coupled radio frequency generator. The invention also includes a capacitor constructed on a conductive surface by the method of the invention.

Abstract: An apparatus for and method of minimizing the thermo-mechanical fatigue of flip-chip packages. The interposer of the present invention, preferably comprising an organic polymer such as polyimide, contains apertures having conductive plugs inserted therein for joining a chip to a substrate in an electronic module utilizing flip-chip packaging. The interposer is selected to provide optimum spacing between the chip and substrate having a coefficient of thermal expansion adapted to the thermal cycling temperature extremes of the module components. The interposer may comprise an inner core with two adhesive outer layers which may comprise different materials to promote adhesion at their respective interfaces within a module. Conductive plugs are disposed within the apertures of the interposer comprising of a first and second solder or comprising a conductive plug having top and bottom surfaces coated with a conductive adhesive.