Abstract: According to an example embodiment, there is method (100) for manufacturing a semiconductor device in an air-cavity package. For a device die having an active surface, a lead frame is provided (5), the lead frame has a top-side surface and an under-side surface, the lead frame has predetermined pad landings on the top-side surface. A laminate material is applied (10) to the top-side surface of the lead frame. In the laminate material, an air-cavity region and contact regions are defined (15, 20, 25, 30, 35). The contact regions provide electrical connections to the predetermined pad landings on the lead frame. With the active circuit surface in an orientation toward the laminate material, the device die is mounted (40, 45). The bond pads of the active surface circuit are connected with ball bonds to the predetermined pad landings on the lead frame. An air-cavity is formed between the active surface of the device die and the top-side surface of the lead frame.

Abstract: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate.

Abstract: In an example embodiment, there is a package substrate (200) for mounting an integrated circuit (IC) device (205). The package substrate comprises an IC device placement area (290) surrounded by pad landings (215). For placing surface mount devices in vicinity of the pad landings, there is a plurality of component pads (235a, 235b, 235c, 235d). The plurality of component pads surrounds the pad landings (215). A plurality of device pins (225a, 225b, 225c, 225d, 245a, 245b, 245c, 245d) surrounds the component pads. One or more of the plurality of device pins, having fine-pitch conductive paths (270), couple the one or more of the plurality of device pins to a set of corresponding pad landings (215) or to a set of corresponding component pads; the fine-pitch conductive paths (270) traverse regions between the plurality of component pads.

Abstract: A process (300) is disclosed to measure predetermined wavelength reflectance spectra of a photo resist coated wafer (305,310,315,320) at a nominal thickness. After coating, the predetermined wavelength reflectance (325,330) is measured and the peak heights and valleys in the vicinity of the predetermined wavelength are tabulated. The relative swing ratio is computed (335) as the average peak height of the spectra at the exposure wavelength. This relative swing ratio is then compared to similar computations on other processes to determine which provides the best critical dimension (CD) control.

Abstract: In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has atop (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined (35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern.

Abstract: The present invention relates to a process that minimizes the cracking of low-k dielectric polymers. In an example embodiment, on a semiconductor substrate (200), there is a method of forming a composite dielectric disposed on a metal layer passivated with plasma deposited silicon oxide SiOx. The method comprises depositing a first layer of a first predetermined thickness of a spin-on dielectric on the metal layer protected with a plasma deposited silicon oxide SiOx. Next a thin stress relief layer of a second predetermined thickness is disposed on the first layer of spin-on-dielectric. Upon the thin stress-relief layer, a second layer of a third predetermined thickness of spin-on dielectric is deposited. Low-k spin-on dielectrics may include hydrogen silsequioxane (HSQ) and methyl silsequioxane (MSQ).

Abstract: In performing testing on Automatic Test Equipment (ATE) it is a challenge to accurately generate and measure RF (radio frequency) power. In an example embodiment, in a test apparatus used for measuring the input and output characteristics of an amplifier, there is a method for determining test program parameters. The method involves calculating input loss from the test apparatus power source to the input of the amplifier, defining an input loss correction factor. The output loss from the amplifier output to the power meter of the test apparatus is calculated, defining an output loss correction factor. Using the input loss correction factor, a real input power level is determined and using the output loss correction factor, a real output level is determined.

Abstract: A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein the silicon nitride/silicon stack (14, 16) includes a top layer of silicon (14) and a bottom layer of silicon nitride (16); performing an etch to the silicon nitride/silicon stack (14, 16) to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack (20) over the stepped seed layer and active region (10).

Abstract: Consistent with an example embodiment, the amount of time required for testing circuits that contain a plurality of different clock domains is reduced. According to the embodiment, during selection of the input test pattern to test logic circuits between a timing sensitive flip-flop in a first clock domain that captures a response that depends on test data in a source flip-flop in a second, different clock domain, account is taken of whether the data in the first flip-flop will change value if it is clocked when the response is captured. If not, it may be assumed that uncertainty about the timing relationship of different clock domains does not introduce uncertainty with respect to the data from the timing sensitive flip-flop, so that the response data at the second flip-flop can be treated as reliable.

Abstract: A system and method for fabricating integrated circuits using four fine alignment targets per stepper shot. The four alignment targets are disposed within the scribe line on each side of a four-sided stepper shot. The targets on opposites sides of the region are located in mirror-image positions. For example, in a square or rectangular region, the targets could be at the mid-point of each side, or at each corner. Because the scribe lines for adjoining stepper shots overlap, a target in one shot will overlay a target from a preceding shot. In a positive resist process, for example, the target resulting from the overlay will be reduced in size by an amount corresponding to the amount of rotational error, if any. However, the target will still indicate the center of the stepper shot, thereby compensating for the rotational error with no further measurements.

Abstract: In photo-lithography, one may assess the effect of flare due to various exposure tools. In an example embodiment, in a photo-lithography process on a photo resist coated substrate, there is a method (600) for determining the effect of flare on line shortening. The method (600) comprises, at a first die position on the substrate and in a first exposure, printing a first mask (610) that includes a flare pattern (110) corresponding to one corner of the first mask (610), and in a second exposure, printing a second mask (620) that includes another flare pattern corresponding to an opposite corner of the second mask. At a second die position on the substrate, a composite mask pattern (630) based on features of the first mask and the second is printed. The printed patterns (640) are developed and measurements (650) are obtained therefrom. The effect of flare (660) is determined as a function of the measurements.

Abstract: A device is for digitally processing an input signal that is susceptible to variations in signal strength. The signal (48) is analog to digital converted into a bitstream signal (47), the bitstream signal representing the input signal by consecutive digital values. The device has a signal strength detection circuit (32) for generating a control signal indicative for an overload condition in which the signal strength exceeds a input range of the analog to digital converter, e.g. a sigma-delta modulator. The signal strength detection circuit detects, in the bitstream signal, a sequence (49,50) of adjacent and equal digital values, the sequence having at least a predetermined length. The circuit detects the overload condition effectively and fast, avoiding the delay of signal strength detection in a digital processor.

Abstract: In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress current of voltage to the respective test block and a plurality of sensor blocks located at successively increasing distances from the respective injector block. Each sensor block includes a PNPN latch-up test structure. The present invention combines the respective advantages of IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.

Abstract: Semiconductor devices may be fabricated using nanowires. In an example embodiment, a conductive gate may be used to control conduction along the nanowires, in which case one of the contacts is a drain and the other a source. The nanowires may be grown in a trench or through-hole in a substrate or in particular in an epitaxial layer on substrate. In another example embodiment, the gate may be provided only at one end of the nanowires. The nanowires can be of the same material along their length; alternatively different materials can be used, especially different materials adjacent to the gate and between the gate and the base of the trench.

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprising a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and four control module fields (A1, A2, A3, A4, B1, B2, B3, B4, C2, C4, D2, D4, E1, E3, F1, F3, G2, H1, J1) are assigned to each exposure field (2), each of which control module fields (A1, A2, A3, A4, B1, B2, B3, B4, C2, C4, D2, D4, E1, E3, F1, F3, G2, H1, J1) contains at least one optical control module (OCM-A1, OCMA2, OCM-A3, OCM-A4, OCM-B1, OCM-B2, OCM-B3, OCM-B4, OCM-C2, OCM-D4) and lies within the exposure field (2) in question and is provided in place of at least one lattice field (3) and is arranged at a mutual minimum distance (K).

Abstract: A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unused banks (70) of registers by selectively gating off clock (74), address (76) and data (78) inputs supplied thereto.

Abstract: In the manufacture of semiconductors, it is often necessary to characterize the effect of line width and line width shape on yield. In an example embodiment, there is a method (200) for randomizing exposure conditions across a substrate. The method comprises generating a list of random numbers (210). A random number is mapped (220) to an exposure field, forming a list of random numbers and corresponding exposure fields. The list or random numbers and corresponding exposure fields is sorted (230) by random number. To each exposure field in the list sorted by random number, an exposure dose is assigned (240). The list is sorted is sorted by exposure field (250).

Abstract: A fuse structure (100) suitable for incorporation in an integrated circuit presents a reduced thermal conduction footprint to the substrate (103). A patterned material stack (102) is formed on a substrate (103) and at least a portion of a material disposed between the substrate (103) and an upper portion of the fuse structure (100) is selectively etched so as to reduce the thermal conduction pathway between the upper portion and the substrate (103). In a further aspect of the present invention, the reduced cross-section of the fuse structure (100) has an increased current density resulting in a lower amount of current being needed to program the fuse.

Abstract: Circuit arrangement for shifting the phase of an input signal, which circuit arrangement consists of two branches whose two output signals are 90° phase-shifted, and use of this phase shifter in a circuit arrangement for suppressing the mirror frequency. The filter systems in the two branches of the phase shifter are implemented in such a way that the phase difference between these two branches is 90°, independent of the frequency of the input signal. In the mirror frequency circuit, a frequency band is amplified or blanked during transmission. The base frequency BF constitutes the center of the frequency band. The amplitude difference is small in the solutions according to the invention. The amplitude difference is improved when the two 90° phase-shifted signals are matched or substantially equalized as regards their amplitude. The matching is performed in that the two signals are rectified and subsequently subtracted from each other.

Abstract: The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a second carrier, exposing a second side of the semiconductor layer. Next, an annealing step is performed as a diffusionless annealing, which has the advantage that the semiconductor layer not only has a substantially even thickness, but also has a substantially flat surface. This ensures the best possible annealing action of said annealing step. Very sharp abruptness of the extensions is achieved, with very high activation of the dopants.