Abstract: In a body-worn personal communications apparatus, for example a wrist-carried wireless telephone, an antenna (102) is a helical or other physically-shortened electric antenna that makes use of the enhanced normal component of electric field close to the body. A microphone (114) can act as a top load to the antenna, thereby enabling the use of a shorter antenna. The antenna (102) may be formed from coaxial cable, enabling it to provide electrical connections between the microphone (114) and transceiver circuitry in the body of the apparatus. By arranging for the microphone (114) to have low impedance at radio frequencies, the coaxial cable acts as an inductive stub and enables the antenna (102) to be further shortened.

Abstract: The communication bus system comprises a plurality of node circuits (10a-d) and a relay circuit (12, 14, 16) coupling the node circuits (10a-d). The relay circuit (12, 14, 16) has a transceiver circuit (124, 164) for relaying messages (21) between the node circuits (10a-d) in a normal mode. The transceiver circuit (124, 164) is powered down in a sleep mode. A detector circuit (120, 160) detects an incoming message (41) when the relay circuit (12, 14, 16) is in a sleep mode. A mode control circuit (122, 162) powers up the transceiver (124, 164) in response to detection of an incoming message (21). Steps are taken that ensure, in the normal mode, that messages (21) will not be relayed in unreadable form. The mode control circuit (122, 162) is arranged to cause the transceiver (124, 164) to relay a remainder (25) of the incoming message (21) after power up.

Abstract: The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured. The method comprises:—forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8),—forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26),—removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).

Abstract: In the case of an electronic communication system (100) having; a) at least one base station (10) having at least one antenna unit (16: 16a, 16b), in particular in coil form, which base station (10) is arranged in particular on or in an object to be secured against unauthorized use and/or against unauthorized access, such as on or in, say, a means of transport or on or in an access system, and, b) at least one transponder station (40), in particular in data-carrier form, having at least one antenna unit (44: 44a, 44b), in particular in coil form, which transponder station (40), c) may in particular be carried with him by an authorized user and/or, d) is designed to exchange data signals (22, 24) with the base station (10), in which case, by means of the data signals (22, 24), e) the authorization for use and/or access can be determined and/or, f) the base station (10) can be controlled accordingly, and in the case of a method of detecting and/or guarding against at least one, in particular external, attack, a

Abstract: A method for manufacturing on a substrate (24) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone (22) in the substrate (24), thereafter forming the floating gate (28) on the substrate (24), thereafter extending the floating gate (28) using polysilicon spacers (40), and thereafter forming the control gate (44) over the floating gate (28) and the polysilicon spacers (40). Such a semiconductor device may be used in flash memory cells or EEPROMs.

Abstract: Method for forming a strained Si layer on a substrate (1), including formation of: an epitaxial SiGe layer (4) on a Si surface, and of: the strained Si layer by epitaxial growth of the Si layer on top of the epitaxial SiGe layer (4), the Si layer being strained due to the epitaxial growth, wherein the substrate (1) is a Silicon-On-Insulator substrate with a support layer (1), a buried silicon dioxide layer (BOX) and a monocrystalline Si surface layer (3), the method further including: ion implantation of the Si surface layer (3) and the epitaxial SiGe layer (4) to transform the Si surface layer (3) into an amorphous Si layer (3B) and a portion of the epitaxial SiGe layer (4) into an amorphous SiGe layer (5), a further portion of the epitaxial SiGe layer (4) being a remaining monocrystalline SiGe layer (6), the amorphous Si layer (3B), the amorphous SiGe layer and the remaining monocrystalline SiGe layer (6) forming a layer stack (3B, 5, 6) on the buried silicon dioxide layer (BOX), with the amorphous Si layer

Abstract: A preferably elongated loudspeaker (LS), which preferably comprises a cylindrical moving coil (SP) and an elongated diaphragm (M) with an elongated fastening part (B) and an annular retaining part (H) lying within the fastening part (B), and with corrugations (S1) extending in radial directions, wherein the diaphragm (M) comprises an arrangement for reducing its stiffness in at least one narrow region (SM1, SM2), which arrangement is present between the fastening part (B) and the retaining part (H). In a preferred embodiment comprising an arrangement of the corrugations (S1) in the at least one narrow region (SM1, SM2) the corrugation density is smaller than the corrugation density in at least one wide region (BM1, BM2). Preferably, the diaphragm (M) furthermore comprises an additional corrugation (S2) in the at least one narrow region (SM1, SM2), which additional corrugation (S2) extends transversely to radial directions.

Abstract: Arrangement for measuring the angular position of an object, using planar magnetoresistive sensors (6, 9) through which an electric current flows and which are arranged in a magnetic field which is parallel to their respective planes, which magnetic field is generated by an arrangement of magnets (4, 14) rotatably journaled eccentrically on a shaft (11), the angular position of the shaft (11) corresponding to that of the object to be measured.

Abstract: There is provided a switching circuit (50) comprising: a transformer (TR1) including at least one winding (P1, S1, S2); a switching device (FET1) coupled between a source of power (60) and the transformer (TR), the switching device (FETI) being coupled to a driving circuits (100) for periodically driving the switching devices (FET1) into conduction to transfer power from the source (60) to the inductive component (TRi). The circuit (50) further includes: a first monitoring arrangement (115) for determining a measure of a magnetizing current present in the transformer (TR1); a second monitoring arrangement for deriving a measure of hard switching occurring in the switching devices (FETI); and a signal processing arrangement (140, 150, 160, 170, 175) for generating a measure of reflected power being transferred through the transformer (TRI) from the measure of the magnetizing current and the measure of hard switching.

Abstract: In the manufacture of electronic devices (22, 22?), e.g. discrete semiconductor power devices or ICs, a reversible bonding tool (10) is used having a bonding tip or wedge (1, 2) at each of its opposite ends (11, 12). After extensive use of the wedge-tip (1) at one end (11) for bonding wires (21), the tip (1) is worn somewhat. Instead of needing to replace the bond tool as in the prior art, the tool (10) in accordance with the invention is then reversed to use the wedge-tip (2) at the opposite end (12) for bonding further wires (20?). Thus, a cost saving is achieved with regard to tool material.

Abstract: A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.

Abstract: The invention relates to a trench MOSFET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field plate electrode (34) is provided adjacent to the sub-channel region (10) 10 and a gate electrode (32) next to the body (12).

Abstract: The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding computer-readable storage medium, which may be used in particular to speed up writing or programming processes in NV code memories of microcontrollers, such as for example smart card controllers. The method consists in extending the instruction set of the controller by so-called MOVCWR (move code write) instructions, which make it possible to write a defined data word (byte) to a defined destination address within an NV code memory. The data word (byte) is here written to the correct position of the cache page register of the respective NV memory and the page address pointer register of the memory is updated with the associated page address. If an MMU (memory management unit) is present, this MOVCWR writing to the cache page register takes place, like MOVC reading or code fetch, under the control of this MMU.

Abstract: Usually, power supplies are not capable of switching off part of the outputs of a main power supply during stand-by. Due to this, stand-by power supplies are used in addition to operation power supplies. Consistent with an example embodiment, a forward converter is provided, including switches in the rectifier circuit thereof. Due to this, the rectifier circuits may be selectively switched on and off. Advantageously, this may allow that the main outputs of such a forward converter are switched off while on stand-by.

Abstract: An integrated circuit with a test interface contains a boundary scan chain with cells (14) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell (14) is also coupled between a respective one of the terminals (16) and the core circuit (10). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells (14) transport data serially along the boundary scan chain while selectable second ones of the cells (14) write or read data that has been or will be transported through the first ones of the cells (14) in the further mode to or from the terminals (16) from or to the scan chain.

Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.

Abstract: Present invention relates to an oscillator circuit comprising: resonator means (102) and, first and second emitter followers (116, 118) being symmetrically coupled to the resonator means and been connected to further emitter followers (120, 122) for providing capacitive loading.

Abstract: Continuous-time filter system with self-calibration means. The system comprises a master control unit (36) and a slave unit with one or more slave filters (27.1-27.n). The master control unit (36) comprises an integrator (30) having circuit elements (33, C) which match those elements of the slave filter (27.1-27.n) that define the slave filter's time constant (?). Furthermore, the master control unit (36) comprises a voltage comparator (35) connected to an output (34) of the integrator (30), the voltage comparator (35) providing an output frequency signal (fcom), and a phase frequency comparator (PFC; 28) providing a control signal (?) as output signal, the phase frequency comparator (PFC; 28) receiving said output frequency signal (fcom) and a reference frequency signal (fref) as input signals. The slave unit comprises said at least one slave filter (27.1-27.n), the slave filter (27.1-27.

Abstract: There is provided a switch mode power supply circuit including at least one inductive component coupled to an associated switching device for cyclically connecting the inductive component to a source of power. The circuit includes a signal output representative of a voltage at a junction of the at least one inductive component to the switching device. The circuit further comprises a hard switching amplitude detector for deriving a measure of hard switching amplitude occurring in operation in the switching device the detector including a signal processing path for receiving the signal output and generating the measure of hard switching amplitude therefrom. The signal path includes: a signal differentiator for imperfectly differentiating the signal output to generate a corresponding imperfectly differentiated signal; and a signal integrator for integrating the imperfectly differentiated signal in a temporally-gated manner for generating the measure of hard switching.

Abstract: A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor. The invention also relates to a display device and an arrangement for controlling a display device, which each comprise a non-volatile semiconductor memory.