Abstract: A semiconductor device comprises a gate electrode (1) and a gate insulating layer (2) both surrounded by a spacer (3) and produced on a surface (S) of a substrate (100) of a first semiconductor material. The device also comprises a source region (4) and a drain region (5) both situated below the surface of the substrate, respectively on two opposite sides of the gate electrode (1). The source region and the drain region each comprise a portion of a second semiconductor material (6, 7) disposed on the substrate (100) and extending between the substrate (100) and the spacer (3). The second material has a melting point lower than the melting point of the first material. The portions of second material (6, 7) constitute extensions of the source (4) and drain (5) regions. The semiconductor device can be an MOS transistor.

Abstract: The present invention relates to an integrated circuit (DEC V) for processing a plurality of data samples (P) of a data signal (I), wherein said integrated circuit is associated with a counter (CT) and comprises means (SIGN M) for computing a signature, said counter (CT) being adapted to trigger and stop a computation of a signature of said data signal (I), said signature being recalculated each time a data sample (P) of said data signal is output by said integrated circuit (DEC V). Use: Video decoder in a set-top-box.

Abstract: An integrated tuner circuit has an arbitrary IF (intermediate frequency) output. The tuner includes an integrated circuit with a fixed-frequency control loop and a matched external variable capacitance Ct, to achieve tracking of a tuned LC band-pass filter with an arbitrary oscillator.

Abstract: A method for adjusting the signal to noise ratio of a receiver comprises measuring the peak power for an RF signal and determining, based on the measured peak power, whether the RF signal power is within a desired operating range. The method further includes adjusting an RF attenuation for the receiver, when it is determined that the RF signal power is not within the desired operating rang. The method further comprises measuring a peak power foe an IF signal, determining based on the measured peak power, whether the IF signal power is within a desired operating range, and adjusting an IF attenuation for the receiver, when it is determined that the IF signal peak power is not within the desired operating range.

Abstract: A driver for a brushless motor (10) is described comprising a static position sensing device (22), a back EMF detector for detecting a back EMF voltage (40), comprising a filter (42). The driver further comprises an output stage (30) with at least three modules (30U, 30V, 30W) for supplying a current to a respective phase coil (11U, 11V, 11W) of the motor (10), and a commutating device (21) for selectively enabling respective modules (30U, 30V, 30W) of the output stage (30) depending on the position ($) of the motor. The selectively enabling is alternated with a commutation frequency (VE). The commutating device (21) is controlled by the static position-sensing device (22) at startup of the motor and by the back EMF detector (40) after the first detected back EMF pulse.

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with a connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. The element is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.

Abstract: An integrated circuit (100) has a plurality of inputs (110) and a plurality of outputs (120). In a test mode, a test arrangement including a plurality of logic gates (140) is coupled between the plurality of inputs (110) and the plurality of outputs (120). The logic gates from the plurality of logic gates (140) have a first input coupled to an input of the plurality of inputs (110) and a further input coupled to a fixed logic value source (150). The fixed logic value source (150) is used to define an identification code of the integrated circuit (100), which can be retrieved at the plurality of outputs (120) when an appropriate bit pattern is fed to the plurality of inputs (110).

Abstract: The cascode circuit comprises a plurality of switching transistors (11) to be protected from high voltage and a plurality of cascode transistors (13) connected to the switching transistors (11). A test node (B?) is arranged between each switching transistors (11) and its cascode transistor (13), and a test transistor (30.1-30.n) is allocated to each test node (B?), its gate being connected to the test node (B?). The sources of the test transistors (30.1-30.n) are connected to a first test point (31) and the drains of the test transistors (30.1-30.n) are connected to a second test point (32). A first voltage (U1) is applied to the first test point (31) and a second, slightly lower voltage (U2) is applied to the second test point (32). A current flow detected between the first (31) and the second (32) test point indicates that at least one of the cascode transistors (13) does not work correctly. Thus, the cascode circuit is testable.

Abstract: A vertical insulated gate field effect power transistor (3) has a plurality of parallel transistor cells (TC3) with a peripheral gate structure (G31, G2) at the boundary between each two transistor cells (TC3). The gate structure (G31, G32) comprises first (G31) and second (G32) gates isolated from each other so as to be independently operable. The first gate (G31) is a trench-gate (21, 22), and the second gate (G32) has at least an insulated planar gate portion (13, 14). Simultaneous operation of the first (G31) and second (G32) gates forms a conduction channel (23c, 23b) between source (16) and drain (12) regions of the device (3). The device (3) has on-state resistance approaching that of a trench-gate device, better switching performance than a DMOS device, and a better safe operating area than a trench-gate device. The device (3) may be a high side power transistor is series with a low side power transistor (6) in a circuit arrangement (50) (FIG. 14) for supplying a regulated output voltage.

Abstract: There is a method of manufacturing a semi conductor device that comprises source and drain regions of a first conductivity type, and a channel-accommodating region of a second, opposite conductivity type which separates the source and drain regions. The device comprises a gate which extends adjacent to the channel-accommodating region. The method includes the steps of etching a trench into the semiconductor body of the device at a location laterally spaced from that of the gate; and implanting a second conductivity type dopant into the body through the bottom of the trench to form a second conductivity type localised region in the drain region. The dimensions and doping level of the localised level of the localised region in the finished device is such that the localised region and adjacent portions of the drain region provide a voltage-sustaining space-charge zone when depleted.

Abstract: Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a macroblock decode module configured to decode a plurality of context adaptive binary arithmetic coding (CABAC) encoded symbols corresponding to a slice without processor intervention.

Abstract: A description is given of an arrangement for compensation of ground offset in a data bus system comprising a plurality of communication devices (2, 10) which are each supplied with an operating voltage (U0) by a voltage source (4; 14), are connected to ground (G1); G2) and have a data bus connection (6; 12) via which they are connected to a data bus line (8). The special thing about the invention is that between operating voltage (U0) and ground (G2) at least one voltage dividing device (R3, R6) is connected whose output is coupled to the data bus connection (12) of at least one communication device (10) and whose voltage dividing ratio is selected such that an offset of the ground (G2) of the communication device (10), whose data bus connection (12) is coupled to the voltage dividing device (R3, R6), is in essence compensated compared to ground (G1) of another communication device (2).

Abstract: A circuit arrangement, method of executing program code and method of generating program code utilize power control instructions (90) capable of dynamically controlling power dissipation of multiple hardware resources (50-60) during execution of a program by a processor (14). Moreover, a processor (14) configured to process such power control instructions (90) is capable of maintaining the power modes of the multiple hardware resources (50-60) to that specified in an earlier-processed power control instruction (90), such that subsequently-processed instructions (90) will be processed while the power modes of the multiple hardware resources (50-60) are set to that specified by the earlier-processed power control instruction (90).

Abstract: In an example embodiment, there is a method (600) for determining an approximately optimal resist thickness comprising providing a first substrate coated with a resist film having a first thickness using a first coat program, (605, 610). The first thickness of resist is measured (615, 620). A second substrate is provided (625) and coated with a resist film using the first coat program. The resist film on the second substrate is exposed to radiation. The reflectance spectrum near the actinic wavelength of the resist film is measured (630). As a function of the periodicity of the reflectance spectrum, an effective refractive index is determined. Based on the effective refractive index, a periodicity of a swing curve of the resist film coated on the second substrate is determined (635). The maxima and minima are determined as a function of the periodicity.

Abstract: A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) in which a semiconductor body (1) of silicon is provided, at a surface thereof, with a semiconductor region (4) of a first conductivity type, in which region a second semiconductor region (2A, 3A) of a second conductivity type, opposite to the first conductivity type, is formed forming a pn-junction with the first semiconductor region (4) by the introduction of dopant atoms of the second conductivity type into the semiconductor body (1), and wherein, before the introduction of said dopant atoms, an amorphous region is formed in the semiconductor body (1) by means of an amorphizing implantation of inert atoms, and wherein, after the amorphizing implantation, temporary dopant atoms are implanted in the semiconductor body (1), and wherein, after introduction of the dopant atoms of the second conductivity type, the semiconductor body is annealed by subjecting it to a heat treatment at a temperature in the range of about 500 to about 80

Abstract: The invention relates to an arrangement for testing integrated circuits, to a test system (2), to a circuit (1) to be tested, and to a method of testing logic circuits, where the test system (2) includes a programmable algorithmic test vector generator (4) which generates test vectors in real time so as to transfer these vectors to the circuit (1) to be tested.

Abstract: In order to develop an electronic communication system (100; 100?), designed for a progressive movement means, having at least one base station (10) and having at least one carrier station (60) such that the possible uses of this communication system (100; 100?) can also be extended to other important areas of use of a progressive movement means, it is proposed that the carrier station (60) be designed as in each case at least one sensor unit, which is assigned to at least one wheel or tire (90) of the progressive movement means and—which is designed to detect and/or determine at least one characteristic parameter of the wheel or tire (90), such as for example the air pressure and/or the temperature and/or the wear of the wheel or tire (90).

Abstract: A circuit arrangement for obtaining an output signal (Va) form a signal (Vs) containing at least one alternating component comprises a signal source (1) that supplies this signal (Vs), a first peak value detection device (2) for determining a maximum value (Vmax) of the signal (Vs), a second peak value detection device (3) for determining a minimum value (Vmin) of the signal (Vs), a first signal linking device (4, 5, 6, 71) for obtaining a first resulting signal (V1) by additive linking of the signal (Vs), the maximum value (Vmax) and the minimum value (Vmin) in accordance with the rule: V1=K1*{Vs?(Vmax+Vmin)/2}, in which K1 is a freely selectable first constant factor, a second signal linking device (7, 72) for obtaining a second resulting signal (V2) by additive linking of the maximum value (Vmax) and a minimum value (Vmin) in accordance with the rule: V2=(Vmax?Vmin)*K2, in which K2 is a freely selectable second factor, a first squaring device (8) for squaring the first resulting signal (V1), a second squar

Abstract: An electronic circuit has an output driver (DRV) for providing a driving signal (U0). The output driver has a transistor (T) with a first main terminal, a second main terminal and a control terminal coupled to receive a control signal (Vcntrl), a power supply terminal (VSS), an output terminal (OUT) for providing the driving signal (U0) that is coupled to the second main terminal, and a sensing resistor (Rm) coupled between the power supply terminal (VSS) and the first main terminal. The output driver (DRV) further has means for temporarily disabling the coupling between the control terminal and the control signal (Vcntrl) during a peak voltage across the sensing resistor (Rm). The means may have a circuit that has a unidirectional current behavior, such as a diode (D), in series with the control terminal of the transistor (T).