Abstract: The invention provides for a delay fault test circuitry for producing a train of two clock pulses in response to two respective clock signals of different frequency associated with logic circuits to be tested and which are arranged to run at different speeds, and arranged such that the rising edges of the second of the clock pulses are aligned and further including counting means for producing a reference count value, means for initiating the first of the two clock pulses when the said count value reaches a first threshold value, means for ending the first of the two clock pulses when the said count value reaches a second threshold value, means for initiating the second of the two clock pulses when the said count value reaches a third threshold value; means for ending the second of the two clock pulses when the count value reaches a fourth threshold value, wherein the third threshold value is common for both input clock signals and the first, second and fourth threshold values are based on the respective freq

Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: A plurality of integrated circuits that are used in an electronic circuit have functional interconnections and dedicated test connections. The integrated circuits receive and transmit synchronization information, such as clock signals from one integrated circuit to another successively through the chain. This permits a high-test speed. Preferably the synchronization information is serialized with test data, test results and/or commands. Preferably, the bit rate between successive integrated circuits in the chain is programmable by means of commands transmitted through the chain. Thus, different bit rates may be at different locations along the chain to reduce the delay occurred by the synchronization signals along the chain.

Abstract: A bias circuit for use in bandgap voltage reference circuits and temperature sensors comprises a pair of transistors (Q, Q2), the first of which (Q1) is arranged to be biased at an emitter current lbias, and the second of which (Q2) is arranged to be biased at an emitter current of m.lbias. The circuit is arranged such that the difference between the base-emitter voltages of the transistors is generated in part across a first resistance means having a value Rbias and in use carrying a bias current equal to lbias and in part across a second resistance means of value substantially equal to Rbias/m and in use carrying a current equal to the base current of the second transistor. This results in use in a bias current Ibias which, when used to bias a substrate bipolar transistor via its emitter, produces a collector current therefrom which is substantially PTAT and a base-emitter voltage which is substantially independent of the forward current gain of the substrate bipolar transistor.

Abstract: Consistent with an example embodiment, there is a method is for powering an integrated circuit. An integrated circuit comprises a chip within a package assembly, the chip includes a plurality of logic circuits each having at least one power input which should not receive a power voltage exceeding a predetermined maximum operating voltage. The method comprises measuring a power voltage supplied to the integrated circuit directly within the chip at the power input of at least one logic circuit. The power voltage is regulated such that the voltage supplied to the power input of at least one logic circuit of the chip is equal to the predetermined maximum operating voltage of this logic circuit.

Abstract: A dc-to-dc converter has two field effect transistors connected in series between an input terminal and a ground terminal. Adjustment of the dead time when both transistors are off is carried out by providing Kelvin feedback connections directly across the drain and source of one or both of the transistors, so bypassing signal line resistance and inductances.

Abstract: In order that an electronic communications system (100) equipped with: [a.1] at least one base station (10), to which [a.2] at least one LC resonant circuit (13, 16) [a.2.1] with at least one antenna unit (16) in the form of a coil, and [a.2.2] at least one capacitive unit (13) series-connected to the antenna unit (16) is assigned, which base station (10) is arranged, in particular, on an object to be secured against unauthorized use and/or against unauthorized access, such as on a means of locomotion, on an access system or on an entry system, and [b.1] at least one transponder station (40), to which [b.

Abstract: In order to provide a method of determining an angle a of an external magnetic field relative to a magnetoresistive angle sensor with two full bridges which respectively supply an output signal U1=U0sin(2?), U2=U0cos(2?), wherein the angle determination can be carried out using simple electronic components, it is proposed that the angle ? is determined in an analog manner using the relation ?=½*(U1/(U1|+U2|))?1*sgn(U2).

Abstract: A method for determining rotational error portion of total misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the rotational error portion of the total misalignment error is determined by measuring the circumferential misalignment between the first pattern and the second pattern.

Abstract: A driver for an inductive load such as a solenoid coil 92 includes three FETs 4,6,8. Two of the FETs are reversely connected between battery and output terminals 16, 18, and one of the FETs is connected between output and ground terminals 16, 14. A driver circuit 10 having high and low side control circuitry 58,56 is formed in a common substrate with two of the FETs 4,6. In use, a coil 92 is connected to the output terminal 16, and driven in an energize mode in which current in the coil 92 is built up as indicated by arrow 100, a freewheel mode in which current circulates freely as indicated by arrow 102, and then may be switched off. The reversely connected FETs allow both short circuits to be prevented in the energize mode and allow the coil to be rapidly switched off. In spite of the control circuitry being formed in a common substrate with some of the FETs, the arrangement allows the FETs to be properly driven.

Abstract: The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semiconductor devices on a substrate (10), each device having a floating gate (36), comprising: first forming isolation zones (14) in the substrate (10), thereafter forming a floating gate separator (32) on the isolation zones (14) at locations where separations between adjacent floating gates (36) are to be formed, after forming the floating gate separator (32), forming the floating gates (36) on the substrate (10) between parts of the floating gate separator (32), and thereafter removing the floating gate separator (32) so as to obtain slits in between neighboring floating gates (36). This method has an advantage over prior art in that less residues of floating gate material, or less floating gate material shorts between adjacent floating gates occur.

Abstract: A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less than the handler wafer (304) and drain, a condition under which prior art SOI devices may not properly operate.

Abstract: As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

Abstract: A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.

Abstract: Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side and the second side, and voltage supply and ground connections mutually arranged according to a chessboard pattern. These connections extend in a direct path through vertical interconnects and bumps to bond pads at the integrated circuit, which bond pads are arranged in a corresponding chessboard pattern. As a result, an array of direct paths is provided, wherein the voltage supply connections form as much as possible the coaxial center conductors of a coaxial structure.

Abstract: In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel region (101), the first stack (6) comprising, in this order, a tunnel dielectric layer (11), a charge storage layer (10) for storing an electric charge and a control gate layer (9), and a second stack (7) of layers on top of the channel region (101) directly adjacent to the first stack (6) in the channel direction (102), the second stack (7) comprising an access gate layer (14) electrically insulated from the semiconducting body (1) and from the first stack (6), initially a first sacrificial layer (90) is used, which is later replaced by the control gate layer (9).

Abstract: An apparatus and method for matched variable resistor structures to electrically measure unidirectional misalignment of stitched masks for etched interconnect layers includes a first test pad and a second test pad for measuring resistance therebetween; a first resistive element electrically connected at a first end to the first test pad; and, a second resistive element electrically connected at a first end to the second test pad. The first resistive element and the second resistive element are electrically connected by a vertical offset. The resistance measured between the first test pad and the second test pad is variable in accordance with an alignment of the first resistive element and the second resistive element relative to the vertical offset. An indicator may optionally provide an indication that the resistive elements are in alignment.

Abstract: A semiconductor device has a channel termination region for using a trench (30) filled with field oxide (32) and a channel stopper ring (18) which extends from the first major surface (8) through p-well (6) along the outer edge (36) of the trench (30), under the trench and extends passed the inner edge (34) of the trench. This asymmetric channel stopper ring provides an effective termination to the channel (10) which can extend as far as the trench (30).

Abstract: Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.

Abstract: A semiconductor device, for example a diode (200), having a pn junction (101) has an insulating material field shaping region (201) adjacent, and possibly bridging, the pn junction. The field shaping region (201) preferably has a high dielectric constant and is coupled via capacitive voltage coupling regions (204,205) to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction (101) and the device is non-conducting, a capacitive electric field, is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region (201), the electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region (208,209) and an increased reverse breakdown voltage of the device.