Abstract: An apparatus for transmitting drive motion to the members working in dispensing devices and seed and fertilizer dosing devices, equipped to vary the speed of such drive motions according to the operative needs present in each dosing, comprising, in combination, at least one velocity sensor arranged correspondingly with one of the machine supporting wheels, which sensor is integrated to an electronic circuit including the Intelligent Central Unit consisting of a microprocessor having its own software which commands the movements generated by a plurality of Propelling Units, integrated to the same circuit and arranged, individually, correspondingly with each dispenser and dosing device of the machine, coupled to at least one of the members belonging to the dosing devices and dispensers involved in the drive movement and action of each of them. Liquid and/or granular fertilizer or seed can be dispensed.

Abstract: The present invention discloses a pointing device having a computer host. The present invention comprises a cursor move device for moving the cursor and a command input device for inputting commands to the computer host. Among these, the computer host further includes a mother board, a CPU, a memory and at least one connecting port. Via the connecting ports, user interface such as a display and a keyboard can be connected to the present invention to form a complete computer.

Abstract: First of all, a semiconductor substrate is provided, and then a photoresist layer is formed and defined on the semiconductor substrate. The pulsed plasma doping is then performed by the photoresist layer as a mask to form a doping region and an undoping region on the semiconductor substrate. After removing the photoresist layer, performing a thermal oxidation process to form a thick gate oxide layer in the doping region and a thin gate oxide layer in the undoping region. Subsequently, two gates are respectively formed on the thick gate oxide layer and the thin gate oxide layer by means of the conventional process.

Abstract: A semiconductor substrate having a source/drain region is initially provided, wherein a channel is formed in the space between the source/drain region within the semiconductor substrate. Then the oxide-nitride-oxide layers are formed on the semiconductor substrate, wherein the nitride layer is a charge trapping layer. Afterward, an electrically conductive material layer such as a gate is formed on and overlays the oxide-nitride-oxide layers. Subsequently, the memory cell is programmed by ultraviolet light irradiation to increase the threshold voltage of the memory cell.

Abstract: The present invention relates to a new strain of Streptomyces sp., called CIMAP A1 isolated from the soil of geranium (Pelargonium graveolens) planted in the experimental fields of CIMAP and having the accession No. ATCC PTA-4131 and capable of inhibiting the growth of phytopathogenic fungi.

Abstract: The present invention provides a method for forming a semiconductor device with a metal substrate. The method includes providing at least one semiconductor substrate; forming at least one semiconductor layer on the semiconductor substrate; forming the metal substrate on the semiconductor substrate and then removing the semiconductor substrate. The metal substrate has advantages of high thermal and electrical conductivity that can improve the reliability and lifetime of the semiconductor device.

Abstract: In accordance with the present invention, a method is provided for dry cleaning a processing chamber. This method comprises the step of introducing a first cleaning process gas into the processing chamber. A plasma is formed from the first cleaning process gas and maintained for a first time period. Next, repeating the step of introducing the cleaning process gas, a second cleaning process gas is introduced into the processing chamber and maintained the plasma for a second time period. As a result, the present invention is capable of removing polymer built up on the processing chamber's interior surfaces to achieve a high yield and maintaining throughput of the substrates in the plasma processing system.

Abstract: A photodetector pixel cell is proposed by the invention. Herein, the presented pixel cell comprises a diode region and a circuit region, and is enclosed by isolation. Moreover, the doped region is existed inside both regions. The structure of the presented pixel cell comprises following characteristics: First, the first well is only located inside the circuit region, where the conductive type of the first well is opposite to the conductive type of the doped region. Second, the second well is located inside the diode region and is contiguous to the isolation, where the conductive type of the second well is equal to that of the doped region. Third, the doped region is not contiguous to the second well, they are separated by uncovered surface part of the substrate. Fourth, the doped region and the substrate provide the diode.

Abstract: A biaxially oriented polypropylene film is described. The n-heptane-insoluble content of the film has a chain isotacticity index, measured by 13-C-NMR spectroscopy, of at least 95%. In particular, the film should have the lowest possible shrinkage (transverse shrinkage and longitudinal shrinkage) at elevated temperatures. In addition, a process for the production of the polypropylene film and its use is described.

Abstract: A salicide integrate solution for embedded virtual-ground memory of the present invention provides a controlled distance between poly gates. In this way, the spacers formed on the sidewalls of the poly gates become self fill-upon spacers, and the surface of the substrate is not exposed. Thus, the salicides will not be formed on the surface of the substrate causing the connection of the buried diffusion regions. Moreover, the present invention provides two dummy poly gates located on the outside of the poly gates, so that the buried diffusion regions on the surface of the embedded virtual-ground memory are covered by the poly gates and self fill-up spacer. Utilizing the present invention, the process of forming salicides on the memory cell region and the peripheral logic region can be integrated together.

Abstract: The present invention provides a method for forming a dual-damascene structure and comprises following steps. First, a substrate is provided. Then, a first low-k dielectric layer and a second low-k dielectric layer are sequentially formed on the substrate. Next, a first via hole is formed in the first low-k dielectric layer by removing a portion of the second low-k dielectric layer and the first low-k dielectric layer. Thereafter a second via hole is formed in the second low-k dielectric layer by removing a portion of the second low-k dielectric layer, wherein the second via hole connects with the first via hole. Then, a conductive layer is formed to fill the first via hole and the second via hole. Next, the second low-k dielectric layer is removed. Last, a low-k dielectric layer is formed on the first low-k dielectric layer and exposes the conductive layer.

Abstract: A method for generating a semiconductor test program is disclosed. The method is practiced by first creating a test plan according to a test key database, then take out the related parameters from the other databases in light of the test item in the test plan and creating a semiconductor test program. The semiconductor test program is attached to the wafer acceptance test (WAT) main program as a sub-program. The method for generating the auto-testing program can promote the efficiency for writing a test program and is easy to expand and maintain according to the progress of semiconductor processes.

Abstract: A method of manufacturing a phase grating image sensor is disclosed. The method uses conventional photolithography and etching methods to form a plurality of phase grating lenses into the conventional flattening layer on which the conventional micro-lens is formed. The invention thus utilizes phase gratings to replace the conventional micro-lens.

Abstract: A method and an apparatus for drying semiconductor wafers by using an IPA drying apparatus. The present invention uses a vapor generator to generate an IPA vapor. The IPA vapor is generated and saved in a closed surrounding and then transferred in a porous hollow plate in the dryer tank by using a quartz pipe. The IPA vapor is diffused evenly from the porous hollow plate. Furthermore, the present invention increases the safety of the process and can easily control the input amount of the IPA vapor.

Abstract: Biaxially oriented films having a substantially non-voided pigmented core layer of a propylene homopolymer, an intermediate layer of a voided propylene homopolymer, and two outer layers of a heat sealable olefin polymer. Such films can be heat sealed to form seals with high seal integrity.

Abstract: A method of measuring the thickness of an epitaxial layer is disclosed. The method is particularly useful in measuring the epitaxial layer with a doping concentration lower than or similar to the substrate on which the epitaxial layer is formed. The method uses a non-single crystal layer previously formed on the substrate before forming the epitaxial layer over the substrate so that the portion of the epitaxial layer on the non-single crystal layer will be polycrystal. To obtain the thickness of the epitaxial layer, thicknesses of the polycrystal layer and the non-single crystal layer as well as the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer are measured. The thickness of the epitaxial layer equals the result of the total thickness of the polycrystal layer plus the non-single crystal layer minus the thickness difference between the polycrystal layer plus the non-single crystal layer and the epitaxial layer.

Abstract: A method of forming floating gates for flash memory is disclosed to improve contact properties with erase gates. The method includes formation of a tunnel oxide layer, a polysilicon layer and an interpoly insulating layer. These layers are patterned in two dry etching steps to complete floating gate definition. In the first etching step, the interpoly insulating layer is etched open in an oxide chamber to form a taper opening. The taper opening is further deepened in the second etching step, in which the polysilicon layer and the tunnel oxide layer are etched open in sequence in a poly chamber. A contact with smooth, vertical surface profile is thus formed in the second etching step. The two-step dry etching procedure is found to provide good contact profile for the floating gate to facilitate subsequent oxide deposition and contact filling. The proposed etching procedure also makes substantial operation reduction for floating gate formation and thus advantageously costs down for flash memory production.