Abstract: In a laptop computer having a display, a matrix of touch-sensitive keys, and a TrackPoint® device for generating cursor and function selection on display is embedded centrally among the keys. The TrackPoint® has a removable cap into which the joystick can be mechanically and electrically coupled. This permits stable platform joystick operation, especially where the computer executes programs involving a joystick as an element of a simulated control interface.

Abstract: A method and apparatus for detecting and correcting errors and erasures in product-coded data arrays by iterative syndrome processing array data in row major order and column major order. A first dense map is formed for classifying each row containing location indicia of random errors, their correction patterns, and pointers to rows containing erasure errors. This map is used to effectuate row array random error corrections in place in memory. A second dense map is formed of location indicia and correction patterns for each pair adjacent position within a column containing erasure errors as indexed by a counterpart row pointer. The second map is used to effectuate column array erasure corrections and random error corrections in place in memory.

Abstract: An apparatus for reducing friction, tearing, or wrinkling of the surface of a single-ply or multiple-ply continuous medium being fed to a processing station by either sprocket engagement of an edge-perforated medium or pinch roller pressure engagement of the medium as the medium moves in a vertically-oriented path, said reduction being effectuated through selectively altering the contact path length of guides supporting the medium in a direction reducing any friction forces.

Abstract: This mechanism relates to a method within the area of information mining within a multitude of documents stored on computer systems. More particularly, this mechanism relates to a computerized method of generating a content taxonomy of a multitude of electronic documents. The technique proposed by the current invention is able to improve at the same time the scalability and the coherence and selectivity of taxonomy generation. The fundamental approach of the current invention comprises a subset selection step, wherein a subset of a multitude of documents is being selected. In a taxonomy generation step a taxonomy is generated for that selected subset of documents, the taxonomy being a tree structured taxonomy hierarchy. Moreover this method comprises a routing selection step assigning each unprocessed document to the taxonomy hierarchy based on largest similarity.

Abstract: A composite encoder/syndrome generating device that both computes check symbols over counterpart data symbol strings to form codewords, and derives syndromes from codewords indicative of their error state. The multistage device provides recursive processing paths at each stage of depth corresponding to the number of symbols concurrently applied to the device. The device is adapted as an encoder when the feed-forward paths between stages are enabled; it is adapted as a syndrome generator upon their disablement. The number of symbols concurrently processed may be varied from clock cycle to clock cycle by conforming the recursion paths per stage to the number of symbols applied as input to the device.

Abstract: A method and a system are presented for generating differentially compressed output from binary sources. Given two versions of the same file as input streams, a compact encoding of one of the input streams is generated, by representing it as a set of changes with respect to the other input stream. Algorithms for differencing files requiring time linear in the size of the input and a constant amount of space for execution are presented. In addition, advanced techniques for improving existing differencing algorithms are developed and applied to previous methods. These techniques allow algorithms to increase their efficiency without a loss of compression and to accept arbitrarily large inputs without sacrificing correctness or degrading the compression data rate. The differential compression methods provide a computationally efficient compression technique for applications that generate versioned data.

Abstract: A machine-implementable method and apparatus for automatic extension of results obtained by querying a database of relationally organized data and expressed in tabular row and column format. The method involves modifying the query by adding column variables to the query that show a high association with the initial query designated variables. The modified query is then used to access the table. This repeats until a stop condition is sensed. Tuples of values elicited responsive to the modified query are included in an extended response if they are significantly similar to tuples elicited by the original query. Several association and similarity modes are described by which the number of variables and tuples can be reiteratively extended.

Abstract: A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t≦5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.

Abstract: A method and means for enhancing the error detection and correction capability obtained when a plurality of data byte strings are encoded in a two-level, block-formatted linear code using code word and block-level redundancy. This is accomplished by vector multiplication of N data byte vectors and a nonsingular invertible integration matrix with nonzero minors with order up to B to secure the necessary interleaving among N data byte vectors to form modified data byte vectors. The selected patterns of interleaving ensure single-pass, two-level linear block error correction coding when the modified data vectors are applied to an ECC encoding arrangement. The method and means are parameterized so as to either extend or reduce the number of bursty codewords or subblocks to which the block-level check bytes can be applied.

Abstract: A generalized method for dynamically deriving configuration information from a set of given parameters for detecting binary-valued sequences from (d, k) partial-response (PR) coded waveforms of predetermined shape, for applying the derived information to configure a processor, and for operating the configured processor as a PR detector.

Abstract: A method and apparatus for high-speed memory management of ECC product-coded data arrays read back from DVD storage subsystems in which rows of length Y≦2N×(2m+1) of the array are read from disk and written in alternate blocks of 2N bytes per block and (2m+1) blocks per row into successive addresses of a synchronous dynamic random access memory (SDRAM) operable both as a buffer and an interleaved pair of memories. Array data is subjected to detection and correction of error and/or erasure by ECC processing of data extracted from and rewritten into the SDRAM, the array being extracted, ECC processed, and rewritten to and from the SDRAM in block interleave column major order and then in block interleave row major order.

Abstract: A method and apparatus for serializing access to disk arrays shareable among a plurality of RAID control units at a substantial reduction in intercontrol unit communication by (a) defining a lock function over the parity image blocks at each of the disk drives of a shared disk array; and (b) executing a path expression at each accessing control unit, the path expression includes requesting a lock from the drive on the parity image and enforcing a busy-wait until a lock is granted, executing the RAID function, and then releasing the lock.

Abstract: A method and means for reducing high-duty-cycle unconstrained binary signal sequences in storage and communications processes and systems by invertibly mapping such sequences into a (1, k) rate ⅔ RLL codestream constrained to a duty cycle substantially approximating one-third. That is, binary sequences ordinarily mapping into high-duty-cycle RLL-code sequences are either inhibited from repeating indefinitely or excluded.

Abstract: A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t.ltoreq.5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.

Abstract: The invention relates to an arithmetic unit (AU) in combination with an algebraic block ECC decoder for controlling errors in an electronically recorded digital data message by performing at least one of a plurality of predetermined arithmetic operations on the data message in one or more of a plurality of subfields of a first GF(2.sup.12) or a second GF(2.sup.8) finite field. The arithmetic operations are selected either from a first group of operations associated with a first subfield GF(2.sup.4) as cubically extended to the first finite field GF(2.sup.12) or as quadratically extended to the second finite field GF(2.sup.8), or selected from a second group of operations associated with a second subfield GF(2.sup.6) as quadratically extended to the first finite field GF(2.sup.12).

Abstract: A method and apparatus in which on-chip functions are checked and any detected anomalies are located within a nested time interval. An on-chip function is tested by (1) applying a predetermined data pattern to the function, (2) computing a linear block error detection code residue from any output from the function being tested, and (3) comparing the residue to a error code residue (signature) derived from the output of a copy of the same function with the same data pattern. In one embodiment, the code signature has been previously derived from an error-free copy of the function. Where the signature is supplied contemporaneously by another copy of the same function also being tested, the function copy is not presumed error free. In both cases, any mismatch between the on-chip code residue and the signature indicates error, erasure, or fault. By either recursive reprocessing or shortening the intervals between comparisons, the mismatch can be located within a nested time or sequence interval.

Abstract: A method and means for detecting and correcting anomalies in a RAM-based FPGA by comparing CRC residues over portions of the RAM-stored connection bitmap with prestored residues derived from uncorrupted copies of the same bitmap portions. A mismatch selectively invokes either error reporting to the chip only, error reporting and immediate verification testing of counterpart FPGA chip functions, or error reporting, parity-based correction of the words in error, reprogramming of the chip functions with the corrected words, and verification testing.

Abstract: A method and apparatus for the recovery of information via asynchronous signal sampling of coded analog waveforms by double interpolating values into the train of asynchronously sampled signals prior to the train being applied to a synchronous detector. The double interpolation includes averaging successive sample signals and midpoint interpolating them between the sample, and then interpolating signals between the sample signals and midpoint signals closest to predicted synchronous points. This double interpolation facilitates low sampling rates while still effectuating accurate synchronous digital detection.

Abstract: A method and system for resolving error or erasure in binary data streams read back using MR heads from a cyclic, multitracked recording medium. The method assesses whether an erasure or error was coincident with a thermal asperity. If the coincidence occurred, the method branches to and executes an ordered list of data recovery procedures tuned to thermal asperity. This list emphasizes early use of burst ECC correction and alteration of MR head and read channel attributes.

Abstract: If consecutive read or write requests imposed on a DASD are of the same type and bear a defined sequential logical address relationship (pure sequential, near sequential), then a circular buffered data path using a pair of a synchronously managed read/write ports respectively coupling either a cyclic, concentric, multitracked storage medium or a cyclic, spiral-tracked storage medium and a device interface can continue data streaming unabated. Otherwise, the path would ordinarily have to be disabled and reconnected using a control microprocessor in respect of any random sequence of requests.