Abstract: A method of manufacturing a semiconductor device provided with a MOS field effect transistor having a channel region of a first conduction type formed in a surface layer portion of a semiconductor substrate, a source region of a second conduction type formed on a rim portion of a trench made to penetrate through the channel region, and a base region of the first conduction type formed in the surface layer portion of the semiconductor substrate adjacently to the source region. The method includes: a step of forming a mask layer having a base-region forming opening corresponding to the base region and a trench forming opening corresponding to the trench on the semiconductor substrate in which the channel region is formed; a base-region forming step of introducing impurities through the base-region forming opening; a trench forming step of forming the trench through the trench forming opening; and a step of forming a gate insulation film on an inner wall surface of the trench.

Abstract: A resin-molded semiconductor device capable of preventing an adhesive from flowing out along conductive paths from where electronic parts are attached on the conductive paths when the electronic parts are fixed to the conductive paths of a semiconductor package. The semiconductor device comprises a semiconductor chip (10), a plurality of conductive paths (12) connected to the semiconductor chip through conductive wires (11) extending from said chip, and an electronic part (13) mounted in such a manner as to electrically connect to two pieces of the conductive paths through the intermediary of an adhesive showing fluidity before hardening and molded in one body the semiconductor chip. In the conductive path, a raised portion is provided to prevent the adhesive from flowing out along the conductive path in the longitudinal direction of the conductive path before the adhesive hardens.

Abstract: An oxidation process is performed for a surface of the SOI film exposed from the opening pattern to form and eliminate the silicon oxide film, so that the SOI film would be thinned. In the opening pattern, formed a gate oxide film as a third insulation film, on which a poly-silicon film is formed as a conductive film so as to fill in the opening pattern. The first insulation film is then eliminated while the second insulation film formed on the inner wall of the opening pattern is remained, so that a gate electrode provided on the side wall thereof with a sidewall would be formed on the gate oxide film.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a first film of silicon nitride or silicon oxynitride on a polysilicon layer, forming a second film of silicon oxide on the first film by chemical vapor deposition, and oxygen-annealing the second film to form a tunnel oxide film. The presence of the silicon nitride or silicon oxynitride film enables an annealing process with a high oxidation capability to be used without oxidizing the polysilicon layer. The leakage of unwanted current through the tunnel oxide film can thereby be reduced, improving the data retention characteristics of devices such as flash memories.

Abstract: A thermal testing control system for notebook computers, remotely controlled by a control means, is described. An enclosure can test notebook computers in its inner space under a predetermined temperature. A temperature sensor, mounted in the testing room is electrically connected to the control means. A blower is mounted in one opening, and electrically connected to the control means. If the temperature measured by the temperature sensor is higher than the predetermined temperature, the blower begins to operate.

Abstract: A semiconductor packgage includes a semiconductor chip provided with a plurality of electric terminals and a plurality of electrically conductive members electrically connected with the electric terminals. Connection terminals that are spherical in shape and made of solder are electrically connected with the electrically conductive members. A sealing member is used for sealing the semiconductor chip and the electrically conductive members, and for covering the connection terminals so as to allow a part thereof to be exposed. The electrically conductive members are provided with bonding promoters and are connected with the respective spherical connection terminals at the respective bonding promoters.

Abstract: A semiconductor storage device in the invention comprises a first control transistor which is connected between a bit line and a first node and whose control terminal is connected to a word line, a data retention circuit which includes a first transistor that is connected between the first node and a second reference voltage terminal, as well as a first inverter that includes a second transistor connected between a second node and the second reference voltage terminal, and a substrate potential control circuit which selectively alters a substrate potential of the first transistor so as to make a threshold voltage of the first transistor higher as compared with threshold voltages of the first control transistor and the second transistor. Thus, it is permitted to provide the semiconductor storage device of static type which realizes a reduced layout area and a lower-dissipation-power operation while ensuring the reliability and high operating speed of the write and read of data.

Abstract: A portable, multi-purpose charging device to charge a primary battery, or one unit or multiple units of secondary battery having same or different voltage than that of the primary battery, and to execute emergency charging to the secondary battery by the primary battery.

Abstract: A clock pulse generator includes an input terminal, an input bias setting circuit, first and second pulse shaping circuit and a pulse combining circuit. The input terminal receives a sinusoidal signal. The input bias setting circuit generates an addition sinusoidal signal having a predetermined bias voltage as a central voltage level thereof. The first and second shaping circuits are connected to the input bias setting circuit. The first shaping circuit has a first threshold voltage that is higher than the predetermined voltage and is responsive to the addition sinusoidal signal to generate a first pulse signal. The second shaping circuit has a second threshold voltage that is lower than the predetermined voltage and is responsive to the addition sinusoidal signal to generate a second pulse signal. The pulse combining circuit synchronizes either of the rising edge or the falling edge of the first pulse signal with that of the second pulse signal so as to generate an output clock pulse.

Abstract: A semiconductor device and a fabricating method thereof, capable of suppressing diffusion of hydrogen into a device and also capable of maintaining high performance are provided, while a passivation film is formed in a device whose performance is easily deteriorated by hydrogen diffusions. The semiconductor device is comprised of: a semiconductor substrate; a ferroelectric capacitor formed on the semiconductor substrate; a first interlayer film containing the ferroelectric capacitor; and a passivation film formed on the first interlayer film; in which a hydrogen diffusion preventing film is formed under the passivation film, and substantially adjacent to this passivation film. Also, the method for fabricating the semiconductor device is comprised of at least a step for forming a hydrogen diffusion preventing film under a passivation film and also substantially adjacent to this passivation film.

Abstract: An input buffer circuit includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage circuit has a P type MOS transistor and an N type MOS transistor connected in series. The succeeding circuit includes inputs connected to the front stage circuit. A logic threshold voltage of the succeeding stage circuit is set to be between the respective logic threshold voltages of the front stage circuits.

Abstract: A motherboard with multiple power selectivity. The components formed on the motherboard comprise a 20-pin ATX power male connector and a 4-pin ATX power male connector. The 20-pin ATX power male connector is coupled electrically with devices and a CPU socket on the motherboard through circuits thereon. The 4-pin ATX power male connector, with four pins configured in line, is applied to provide individual +12 volts/ground/ground/+5 volts power. The 4-pin ATX power male connector is coupled electrically with the CPU socket.

Abstract: A display apparatus comprising first, second, and third scan lines in parallel, first data line perpendicular to the scan lines, first pixel coupled to the first data line, the first scan line, and the second scan line respectively, a second pixel coupled to the first data line and the first scan line respectively, a third pixel coupled to the first data line and the second scan line respectively, and a fourth pixel coupled to the first data line, the second scan line, and the third scan line respectively. The first pixel and the third pixel are on the same side of the first data line and the second pixel and the fourth pixel are on the other side of the first data line.

Abstract: A semiconductor laser device including a lower cladding layer stacked on a compound semiconductor substrate, an active layer stacked on the lower cladding layer, an upper first cladding layer stacked on the active layer, a ridge-shaped upper second cladding layer provided on the upper first cladding layer, current blocking layers provided on both sides of the upper second cladding layer, and a contact layer provided on the upper second cladding layer. The distance between the upper surface of the active layer and the upper surface of the upper second cladding layer is shorter than the distance between the lower surface of the lower cladding layer and the lower surface of the active layer.

Abstract: Circuitry for detecting tonal signals, each of which has a particular nature in the frequency or time domain, while distinguishing them from each other. A rough frequency analyzer roughly analyzes an input signal in an entire frequency band with lower accuracy in the frequency or time domain, thereby roughly distinguishing the tonal signals. Detectors, each of which is associated with a subband occupied by a particular target tonal signal, detect the attribute of the power variation of the target tonal signal with respect to time with higher accuracy in the direction of the frequency or time domain to thereby finely identify the target tonal signal. A controller selectively enables and disables the detectors in accordance with the results from the detectors. One of the detectors is enabled which is selected under the control of the controller.