Abstract: An airflow channel module for oxygen concentrator is provided, including at least two molecular sieves, an oxygen storage unit, an air expelling unit, an air channel module, an air intake/expel module, and an automatic valve. The airflow channel module utilizes the oxygen storage channel and the air channel hidden inside the air channel module, the air intake channel, the air expelling channel and the air supply channel hidden in the air intake/expel module, and the automatic valve to control the flow of the air, oxygen and the nitrogen. By modularizing the airflow channel and eliminating the exposed hoses in conventional oxygen concentrator, the airflow channel module simplifies the assembly and maintenance of the oxygen concentrator.
Abstract: An image-capturing semiconductor device is provided with a simplified constitution and by means of fewer steps than conventional techniques. In a semiconductor device which is packaged at substantially identical outer dimensions to the outer dimensions of a first semiconductor chip, first pads serving as electrode pads are formed along a main surface of the semiconductor chip so as to be electrically connected to a circuit element provided on the semiconductor chip. A sensor portion is formed on the main surface such that a light-receiving surface thereof is exposed. A glass plate for transmitting incoming light to the sensor portion is formed in a position covering the light-receiving surface of the sensor portion. A wiring layer is formed so as to extend over the main surface of the first semiconductor chip and such that one end thereof is connected to the first pads. Solder balls are electrically connected to the first pads via the wiring layer.
Abstract: According to the present invention, a method for creating a sample for a TEM (Transmission Electron Microscope) observation comprising: forming an observation surface at a specific area of a semiconductor device; forming an amorphous protection film on the observation surface; and thinning a portion of the semiconductor device including at least the protection film.
Abstract: A semiconductor device has a semiconductor substrate with an inclined through hole extending between its two major surfaces in a peripheral part of the substrate, providing an electrical interconnection between the two surfaces. The opening of the inclined through hole on the first major surface, on which electronic components are formed, is closer to the edge of the substrate than is the opening on the second major surface. Reliability is therefore enhanced because cracks forming at the edge of the second major surface are less likely to propagate to the through hole. An electrically conductive path in the through hole is formable by spraying conductive material onto its inner wall, using an ink-jet system.
Abstract: A semiconductor structure includes (a) a semiconductor substrate having a channel region and a first integrated impurity diffusion region including a first electric field reduction region that is formed adjacent to the channel region and which includes a plurality of specific regions separated from each other, (b) a first insulating film formed on the semiconductor substrate, and (c) a first electrode structure having a first region formed above the channel region and a second region that is formed adjacent to the first region and above the first electric field reduction region to be self-aligned with the first electric field reduction region, the semiconductor structure including one or more openings formed above the plurality of specific regions and a first opening surrounding portion surrounding the one or more openings.
Abstract: Communicating nodes in a network exchange state variable signals indicating the timing of periodic operations performed at the nodes. Each node autonomously controls the timing of its periodic operation so as to distance the timing from the timing of the periodic operations performed at other nodes. If the periodic operations include data transmission, this arrangement enables the nodes to avoid data collisions. The nodes can also adapt autonomously to changing conditions such as changing priority levels and the addition and removal of nodes.
Type:
Grant
Filed:
September 14, 2004
Date of Patent:
April 21, 2009
Assignees:
Oki Electric Industry Co., Ltd., Campuscreate, Co., Ltd.
Abstract: A toner container (101) is detachably attached to a developing device (104). A toner (120) stored in the toner container (101) is supplied through a supply opening (104a) to a hopper (105) of the developing device (104). A movable shutter (123) is provided below the supply opening (104a). The shutter (123) opens the supply opening (104a) when the amount of the toner (121) in the hopper (105) is less than a predetermined amount, and closes the supply opening (104a) when the amount of the toner (121) in the hopper (105) is greater than or equals to the predetermined amount.
Abstract: LEDs (7) are arranged on at least opposite two corners of a bottom surface of a box body (11) of a tray shape whose bottom surface is quadrilateral, whose upper side is open, on an inner surface of which a light reflection member (11b) is provided, and whose side walls (11c) are inclined outward, so as to irradiate inside of the box body, wherein a plurality of LEDs (71) are arranged so that a region irradiated by each of the LEDs (71) rotates sequentially in a specific direction (same direction). As a result, there can be obtained a surface light source having high brightness and uniformity in an arbitrary size whether the light source is small or large while using semiconductor light emitting devices (LEDs), and an electrically illuminated signboard using the surface light source, which is thin and capable of uniform display and which operates with low electricity consumption.
Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.
Abstract: A semiconductor chip according to the present invention is a semiconductor chip having a circuit forming region, in which an internal circuit including a function element is formed, on the middle portion of the surface thereof, and having the surface thereof opposed to and joined to the surface of a solid-state device.
Abstract: A navigating method for a cell phone with a positioning device and the apparatus thereof are described. The longitudinal and latitudinal coordinates of a guiding mobile in a global positioning system (GPS) are sent to a guided mobile via a short message service (SMS). After decoding the short message contents, the longitudinal and latitudinal coordinates are obtained by the guided mobile. And a navigation application is wakened and launched to perform a navigation function by establishing the longitudinal and latitudinal coordinates as a navigation destination.
Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
Type:
Grant
Filed:
December 28, 2006
Date of Patent:
April 7, 2009
Assignee:
Industrial Technology Research Institute
Abstract: A package structure for a semiconductor device comprises a substrate having a main surface and a back surface, a semiconductor chip formed on the main surface of the substrate, a package covering the semiconductor chip, radiation protrude electrodes and connection protrude electrodes. The radiation protrude electrodes are formed on the back surface of the substrate in a chip area where said semiconductor chip is located. Each of the radiation protrude electrodes are formed with a first pitch so that the radiation protrude electrodes make one body joining layer when the package structure is subjected to a heat treatment. The connection protrude electrodes are formed on the back surface of the substrate in a peripheral area of the chip area. Each of the connection protrude electrodes formed with a second pitch which is larger than the first pitch so that the connection protrude electrodes stay individual when the package structure is subjected to a heat treatment.
Abstract: A method of plating on a glass substrate allowing an electroless plating film with good adhesiveness to be formed by chemically bonding a silane coupling agent in a state of simple adhesion or hydrogen bond to the surface of the glass substrate through dehydration condensation reaction, and a method of manufacturing a magnetic recording medium using the plating method. In the plating method, electroless plating is performed on a glass substrate after sequentially conducting at least the adhesion layer formation that forms an adhesion layer using a silane coupling agent solution, catalyst layer formation, a catalyst activation, and a drying that chemically bonds the silane coupling agent in the adhesion layer to the surface of the glass substrate.
Type:
Grant
Filed:
November 29, 2005
Date of Patent:
April 7, 2009
Assignee:
Fuji Electric Device Technology Co., Ltd.
Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a first region by selectively ion-implanting a second conductive type impurity into a first conductive type semiconductor layer without thermally diffusing an impurity, (b) forming a gate electrode including an edge vicinity region that is aligned with the first region in the horizontal position, and (c) forming a body layer including the first region and a second region that is formed adjacent to the first region and self-aligned with the first region and an edge of the gate electrode by forming the second region with a step of selectively ion-implanting a second conductive type impurity into the first conductive type semiconductor layer without thermally diffusing an impurity.
Abstract: A block interleaving apparatus for block interleaving M-bit input streams to be transferred with a modulus k using a mixed radix system in a multi-band orthogonal frequency division multiplexing communication system, including an array processor having an array including M cells in which the number of columns is k and the number of rows is M/k. The array processor inputs the input streams from the bottom-right cell up to the top-left last cell in the horizontal direction, and, after the first bit of the input streams reaches the last cell, generates interleaved output streams by changing the output of the array processor from horizontal direction to vertical direction.
Type:
Grant
Filed:
November 2, 2007
Date of Patent:
March 31, 2009
Assignee:
Mewtel Technology Inc.
Inventors:
Young Sun Han, Peter Harliman, Seon Wook Kim, Byung Gueon Min
Abstract: An emergency electric power supply unit (9) for backing up the main electric power supply system (1, 10) at the time of the malfunction of the main electric power supply system (1, 10) which includes an industrial apparatus operated by cooperatively controlling an auxiliary machinery (2) operated by the electric power supplied from the main electric power supply system (1, 10), an auxiliary electric power supply (20) for storing the electric power, a charging circuit (21) for charging the electric power supplied from the main electric power supply (1) in the auxiliary electric power supply (20), a discharging circuit (22) for supplying the electric power charged in the auxiliary electric power supply (20) to the auxiliary machinery (2), and an emergency controlling circuit (40) for controlling the discharging circuit (22) so that the electric power from the auxiliary electric power supply (20) is supplied to the auxiliary machinery (2) at the time of the malfunction of the main electric power supply system (1
Type:
Grant
Filed:
November 29, 2005
Date of Patent:
March 31, 2009
Assignees:
Kayaba Industry Co., Ltd., Ashitate Electric Co., Ltd.