Abstract: A speech encoder is disclosed quantizing speech information with respect to energy, voicing and pitch parameters to provide a fixed number of bits per block of frames. Coding of the parameters takes place for each N frames, which comprise a block, irrespective of phonemic boundaries. Certain frames of speech information are discarded during transmission, if such information is substantially duplicated in an adjacent frame. A very low data rate transmission system is thus provided which exhibits a high degree of fidelity and throughput.

Abstract: A constant-voltage regulated power supply circuit has an input circuit and an output circuit. The sense circuit includes a programmable sense circuit that further includes a divider network with a plurality of selectable tap points and a multiplexer having a plurality of inputs and an output with each tap point being connected to an individual input of the multiplexer. A controllable pass element is operatively connected in the power supply circuit between the input circuit and the output circuit. A comparator connected to receive inputs from a selected tap point and a reference voltage generating circuit provides an output to control the controllable pass element.

Abstract: Device for the testing and checking of the operation of blocks within an integrated circuit, characterized in that it is formed from a set of shift registers and logic circuits associated with each block of the circuit to be tested, the set of registers including at least one test register (35), one status register (36) and one mask register (37), the status register (36) being connected to the outputs (ST0 to ST15) of the block to be tested while the test and mask registers (35,37) and the logic circuits (38,39) are connected to a central processing unit (1) of the integrated circuit of which the blocks form part, the central processing unit (1) being also connected to the said blocks (7,10) by a common interrupt line (.SIGMA.INT).

Abstract: The specification discloses a method of transforming input symbolic data to output symbolic data for use in text-to-speech and other environments. A string of digital byte values representing the input symbolic data is stored in a first buffer memory location in rules processor (10). A set of rules defining a desired mapping of byte values is stored in a rules storage (12), along with a set of user special symbols. The rules ae sequentially mapped to transform the stored byte values in accordance with the rules and the special symbols from a first buffer memory location to a second buffer memory location.

Abstract: A sense amplifier circuit is described for switching plural inputs at high speed. At least two transistors for providing at least two true input signals are connected in parallel and have their source terminals connected to a common node from which an output signal may be read. Similarly, at least two other transistors for providing the inverse of the true input signals are connected in parallel and their source terminals are connected to another common node from which an inverse of the output signal may be read. The common nodes are then precharged to the same voltage. True and inverse input signals are applied to their respective transistors through transfer gates where all the true input signals are greater than their respective inverse signals. Therefore, the on-resistance of each of the transistors to which a true input is applied have a higher on-resistance than the associated transistors to which an inverse input is applied.

Abstract: A semiconductor charge-coupled device is fabricated with use of a layer of a doped semiconductor having an insulator layer thereon. Suitable dopant ions such as nitrogen or argon ions are implanted into the doped semiconductor layer so that the projected range of the ions introduced into the semiconductor layer is located substantially at the interface between the doped semiconductor layer and the insulator layer for forming an interlevel layer providing an increased surface state at the aforesaid interface. Where the interlevel layer is formed by implantation of nitrogen ions the structure having the nitrogen ions implanted into the doped semiconductor layer is preferably annealed at a relatively high temperature. The charge-coupled device may be designed either as the surface-channel type or as the buried-channel type with a single-phase, two-phase, three-phase or four-phase driving scheme.

Abstract: Charged particles from a line emitter are focussed as a line image on a means for selectively blocking part of the image to produce a flat beam of controllable length. The blocking means may be an apertured plate with means for rotating and/or translating the image relative to the aperture to produce the required beam length. After passage through the aperture the beam may be twisted and/or translated to its original or some other orientation and position. The beam may be of electrons or ions and may be used in the manufacture or testing of integrated circuits. An alternative form of blocking means is a row of controllable gate electrodes which can block selected parts of the line beam; this is of particular value in producing c.r.t. displays.

Abstract: The present invention is a speech encoding technique useful in low data rate speech. Spoken input is analyzed to determine its basic phonological linguistic units and syllables. The pitch track for each syllable is compared with each of a predetermined set of pitch patterns. A pitch pattern forming the best match to the actual pitch track is selected for each syllable. Phonological linguistic unit indicia and pitch pattern indicia are transmitted to a speech synthesis apparatus. This synthesis apparatus matches the pitch pattern indicia to syllable groupings of the phonological linguistic unit indicia. During speech synthesis, sounds are produced corresponding to the phonological linguistic unit indicia with their primary pitch controlled by the pitch pattern indicia of the corresponding syllable. This achieves some measure of approximation to the primary pitch of the original spoken input at a low data rate.

Abstract: An apparatus and a method for monitoring the functioning of an integrated circuit in operation using an electron beam directed to a particular node of the circuit which is of interest and measuring the energy of the secondary electrons emitted, in which the energy measurement is made using a filter grid, the bias on which is set by comparing a voltage representing the rate of receipt of secondary electrons past the filter grid with a reference voltage and adjusting the bias in response to the comparison so as to reduce the number of electrons received. A current is produced proportional to the difference between the two voltages and applied to charge a capacitor, the voltage on which is used to set the voltage on the filter grid.

Abstract: Speech is analyzed for phonological linguistic units (phonemes or allophones), along with their duration pattern and pitch pattern contour as a group or string of a syllable. The patterns are encoded as the best-match pattern in a set of prestored standard patterns. This data is transmitted to a synthesizer to help in the intonation reconstruction of speech.

Abstract: A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer.

Abstract: The present invention loads color registers of a color look up table in a color palette and recalls color data words from the color registers using only a single set of address and data channels. The color palette operates in two modes. In a normal mode one color code from a stream of pixel color codes received from a pixel map memory is employed to select one of the color registers. These color registers store color data words which define colors. A color data word stored in a selected color register is recalled and employed to control the color of a pixel on a raster scan video display. In a color look up table load mode, a predetermined number of the pixel color codes are loaded into the color look up table in a predetermined sequence, thereby defining a new set of colors. This technique multiplexes the existing data and control lines from the memory to the color palette for the two modes.

Abstract: A system which interprets the contents of address and data fields provided by a central processing unit 1 which controls the display. The address fields are selectively interpreted to obtain a direct access by the central processing unit to a general system memory 5, or so as to constitute instructions for a video processor 2. In this latter case, the address controls an operation cycle of a first priority for controlling the processor or executes a series of operations with a lower priority, such lower priority operations allowing processor 2 to process image information without the intervention of the central unit. The invention finds application in such areas as teletext systems and video games.

Abstract: A static memory cell including a pair of field-effect transistors, characterized by the provision of highly dielectric layers in combination with the field-effect transistors, wherein each of the highly dielectric layers is located directly on a polysilicon gate electrode layer formed on a silicon dioxide insulating layer bridging the channel region of each of the field-effect transistors. The gate electrode layer of one field-effect transistor is held in direct contact with the drain region of the other field-effect transistor and the two highly dielectric layers are covered with a polysilicon conductive layer electrically connected to a supply voltage source so that each field-effect transistor has its drain region connected to the supply voltage source through one dielectric layer and its gate electrode layer connected to the voltage source through the other dielectric layer.

Abstract: The present invention provides an artificial pitch contour to phonological linguistic phoneme unit string data. In the event that the phonological linguistic string data includes some information on intonation contour, such as primary accent, secondary accents and rising or falling intonation mode data, this data is employed along with a determination of syllable type for each syllable to assign one of a predetermined plurality of pitch patterns to each syllable. If such intonation data is not available, as for example in a bar code or text-to-speech system, then primary and secondary accent data are generated based upon the presence or absence of strong vowels involved in word stress syllables. This invention is most useful in improving the spoken intonation contour in low data rate speech applications in which some intonation data is available.

Abstract: A digital filter for synthesized speech includes a full adder (72) that is multiplexed to perform multiplication and addition/subtraction operations. The inputs of the adder (72) are multiplexed by multiplexers (90) and (92). The adder (72) calculates Y-values and B-values. The B-values are input to a delay stack (116) and the Y-values are stored in a Y-register (78). One product is generated of a multiplier stored in a K-stack (128) and a multiplicand selected by a multiplexer (122). The multiplicand is a prestored summation that was earlier stored in a sum register (82). This product is stored in an ACC register (74) and utilized in both the calculation of the B-values and the Y-values. Therefore, only one multiplication is required for corresponding Y- and B-values, thereby reducing the number of multiplication steps required in processing each stage of a digital filter.

Abstract: A process for making a metal fuse link in a MOS or CMOS process which includes depositing a refractory metal or metal alloy over an already deposited multi-level oxide and patterning the deposited metal or metal alloy so that it has a fusing segment between and integral with expanded segments such that the length and cross sectional area of the fusing segment is sufficiently small so that the fusing current therethrough is less than 20 milliamperes. The fuse and surrounding circuitry is covered with a passivation layer and contacts formed in the passivation layer to the expanded segments.

Abstract: Speaker-independent word recognition method and system for identifying individual spoken words based upon an acoustically distinct vocabulary of a limited number of words. The word recognition system may employ memory storage associated with a microprocessor or microcomputer in which reference templates of digital speech data representative of a limited number of words comprising the word vocabulary are stored. The word recognition system accepts an input analog speech signal from a microphone as derived from a single word-voice command spoken by any speaker. The analog speech signal is directed to an energy measuring circuit and a zero-crossing detector for determining a sequence of feature vectors based upon the zero-crossing rate and energy measurements of the sampled analog speech signal.

Abstract: A method for recognizing and providing an output corresponding to a character in which the character is received by an imager, digitized, and transmitted to a memory. Data in the memory is read in a sequence which circumnavigates the test character. Only data representative of the periphery of the character are read. During the circumnavigation, character parameters, such as height, width, perimeter, area and waveform are determined. The character parameters are compared with reference character parameters and the ASCII code for the reference character which matches the character is provided as an output.

Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.