Abstract: A GaAs monolithic true logarithmic amplifier which includes at least one amplifier stage common to the two arms of the circuit, the two arms being independent thereafter, one having lower gain and higher compression point and the other arm having higher gain and lower compression point. The signals in the arms are then recombined off-chip to provide the same effect as in the prior art. The circuit includes an input stage which amplifies and gain shapes the input signal and then splits the signal into upper and lower paths. The upper path is a relatively lower gain and higher compression point path whereas the lower path is a relatively higher gain and lower compression point path. The upper path includes a FET with a very large gate width whereas the lower path includes plural cascaded FETs, the last of which has a very small gate width.

Abstract: A reflective beam of light is used to analyze the optical transmission properties of a developer fluid during puddle develop of photoresist polymer for detercting the process endpoint.

Abstract: A silicon dioxide film containing additional silicon in the form of segregates having controlled grain sizs is fabricated by forming a silicon dioxide, injecting silicon ions into the silicon dioxide film by ion implantation with a predetermined ion acceleration energy and a predetermined ion dose, and annealing the resultant silicon dioxide film for causing the additional silicon atoms in the silicon dioxide film to segregate therein to form segregates of silicon having grain sizes which are substantially predominated by the predetermined ion acceleration energy and the predetermined ion dose.

Abstract: The position of an end "1" bit in an input number is detected by applying the inverted bits in parallel to inputs of respective NOR gates (61 to 68), the other inputs of which are connected to the nodes of a chain of dynamic field effect transistors (A1 to A8) along which a "O" is propagated. The coincidence of two O's at the inputs of a NOR gate causes it to produce a "1" output representing the location of the end "1" of the input number. The outputs of the NOR gates (L1 to L8) are connected to the column conductors of an field effect transistor array (LA) which produces on the row conductors array in parallel, inverted, binary coded form a number corresponding to the position of the NOR gate producing a "1" output. The apparatus may be divided into several units (U1 to U4) responsive to adjacent groups of the bits of the input number each producing a representation of the location of the end "1" in its group.

Abstract: The invention relates to a field-effect transistor (1;20) with insulated gate electrode (9;30) which comprises in a semiconductor body (5) a drain diffusion zone (2) connected to a drain electrode (6;32) and a source diffusion zone (3) which is disposed spaced from the drain diffusion zone (2) for forming a channel zone (4) and which is connected to a source electrode (7). The gate electrode (9;32) of said field-effect transistor is disposed on a gate insulating layer (8) over the channel zone (4). For protecting the transistor against high voltages produced by electrostatic charging the drain diffusion zone (2) of the transistor and/or the source diffusion zone (3) between the respective associated electrode (6,7;32) and the channel zone (4) is divided into a plurality of parallel strips (10,11). Integrated circuits are also protected against destruction by high voltages if the insulated gate field-effect transistors connected to their output terminals are constructed in the manner outlined above.

Abstract: A display system for visually indicating stanby operations belonging to a set of hierarchal processing operations to be carried out by an eletronic data processing apparatus, such as an electronic computing machine, wherein the display system includes a plurality of operation data registers for temporarily storing certain standby operations of the set of hierarchal processing operations to be carried out by the electronic data processing apparatus. A microprocessor controller is operably associated with the operation data registers and determines the priority order of the processing operations which are to be represented by data as stored in the operation data registers the priority order being in accordance with a predetermined hierarchal rule. Thus, the data is arranged in the operation data registers in the order of priority of the standby operations represented thereby.

Abstract: A method of and a circuit for generating address signals, wherein a binary index signal and a binary base address signal are stored in index and address registers, respectively, whereupon the index signal and the base address signal are added together to produce an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation. The initial output address signal is tentatively storing in the address register and is added to the index signal to produce an output address signal differing in bit pattern from the initial output address signal during the cycle of signal generating operation immediately subsequent to the initial cycle.

Abstract: The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

Abstract: Speech recognition is improved using reference pattern templates which have an added noise signal (noise floor) to avoid LPC high-gain synthesizer instability at low signal levels. Also, input signal frames have a length one-half that of reference frames whereby dynamic time warp computation steps are cut almost in half.

Abstract: A communications system employs a multiline bus including control lines for multiple functions in order to minimize the required number of bus lines. This technique is most applicable to small computer systems which are hand portable or briefcase portable and which operate with small peripherals. The transmitting device places an active signal on a handshake line for a predetermined period of time. The receiving device detects this active signal and also places an active signal on the handshake line. The transmitting device applies valid data to the data lines throughout the period that a active signal is on the handshake line. Upon detection of the data the receiver releases the handshake line. Using this technique a single line is used to indicate valid data transmission and proper reception. An additional bus available line, used by a master device to alert slave devices that communications are in process, can be employed by at least some of the slave devices to request service from the master device.

Abstract: A semiconductor integrated circuit device including a signal line connected at one point thereof to a source of a signal voltage variable between high and low levels and a source of an activating signal variable between high and low voltage levels, wherein at least one signal amplifier circuit is operatively connected to the signal line. The signal amplifier circuit is responsive to the activating signal for allowing the signal line to connect to the source of the activating signal in response to the high level of the signal voltage on the signal line in the presence of the activating signal of the high voltage level and maintaining the signal line disconnected from the source of the activating signal in response to the signal voltage of the low level on the signal line.

Abstract: A method and apparatus for storing a relationship between individual elements of two or more knowledge sets includes a main computer (12) that is operable to receive a portable memory cartridge (20). The computer (12) has an input keypad (16), a storage medium (18) and a display (14). A coordinate transducer (24) is provided to input the coordinates from a test sheet (26). The test sheet (26) has a pattern of knowledge elements in a question and answer format. The relationship between the questions and answers is predetermined and is stored in the portable memory cartridge (20). The coordinate transducer (24) provides for input of the coordinates of the question and answer on the test sheet for storage in the computer. After storage, selection of the coordinates of a particular question is followed by selection of the coordinates of an answer and comparison made by the computer (12) with the stored relationship in the portable cartridge (20).

Abstract: This system includes a composite memory (5) in which are memorized the data for images to be displayed for each frame. A video display processor (12) controls the screen (8). A central processing unit (1) effects the composition of the image with the memory and an address processor (10), the extraction of the point data to be displayed being effected by a time base circuit (BT) synchronized with the sweeping of the screen, and by a control device (15) for dynamic access which distributes the access times among different units utilizing the memory. The memory (5) includes a first control memory for the memorization of a data word for a line or group of lines making up the image, each word having an address value for addressing a second control memory which contains, at each of these addresses, at least one display attribute data word characterizing the contents of the line(s) corresponding to the value of the respective address of the first control memory.

Abstract: The present invention involves an improvement in color palettes which translate pixel color codes into color data words which have differing bits. In the color palette a stream of pixel color codes from a pixel map memory enables sequential selection of one of a set of color registers. The color data word stored in the selected color register controls the color of the current pixel within the video display. The innovation of the present invention is providing at least one color data word within the color palette which has no corresponding color of its own but which enables a repetition of the previous color. The entire visual image can be redefined by merely changing the pixel color codes at the first scanned edges of color regions if the entire pixel map memory is filled with pixel color codes which refer to repeat color data words. Hidden objects formed in the pixel map memory can be made to appear or disappear by redefining the color data words in the color registers.

Abstract: A semiconductor heat-treating apparatus comprising a heat treatment furnace main, gas discharging means surrounding the port for carrying semiconductors into or out of said furnace main therethrough, an internal cylindrical partition of said gas discharging means, said internal cylindrical partition engaging fittedly with said port for semiconductors, said gas discharging means being provided with a gas-stream forming system for discharging gases and a second gas-stream forming system for supplying inert gas into said cylindrical partition on the one side thereof and allowing the inert gas together with the gases from said furnace main to exit therefrom.

Abstract: An electron beam apparatus in which the electron beam is directed to a sample and secondary electrons from the sample return in the direction of the beam and are deflected sideways to a collector by a first electrostatic deflection means. To compensate for distortion of the spot produced by the beam as a result of the first electrostatic deflection means, a similar deflection means is placed above the first means to correct the distortion and is so biased as to reflect secondary electrons which might otherwise pass the first means. The deflection means are 4-pole electrostatic stigmators. A threshold grid is biased to allow to pass to the first means only those secondary electrons having release speeds from the sample above a certain value.

Abstract: Calculator having a keyboard in which one or more keys have labels created by a display and subject to changing interactively as the user desires. Typically, advanced scientific-programmable calculators may have too many functions to be adequately included on the keys of the keyboard associated therewith. In such calculators, certain functions require a plurality of keys to be actuated in order to be performed. Thus, such keyboards tend to be cluttered an confusing to the user. Thus, a keyboard is proposed having a small number of keys labeled with different functional labels as the user proceeds through a menu or tree structure containing all the desired functions. Keys in a certain group of keys on the keyboard are thereby subject to redefinition or relabeling so as to provide a variety of functions.

Abstract: A microprocessor based system (10) includes a central processing unit (CPU) (12) that controls the operation of a display (20) through a controller (22). System storage is provided with a read only memory (16) and random access memory (14). A reference clock signal is generated by a clock generator (26) which is input to a clock control circuit (24). The control circuit (24) generates a CLK signal that is connected to the clock input of the CPU (12). The control circuit (24) is operable to reduce the rate of the clock input to the CPU (12) when accessing the controller (22) which has a slower speed of operation than the random access memory (14). The control circuit (24) includes a programmable counter (38) for generating a gating signal after counting a predetermined number of cycles of the reference clock signal and initiating a count cycle only after generation of the gating signal.

Abstract: An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. The number of transistors needed in the decoder for the row select function is greatly reduced by employing predecoders which perform a 1-of-4 select for each pair of address bits, then using one of these select outputs to activate N multiplexers, and all the others as inputs to a decoder with N outputs to the multiplexers.

Abstract: A multiport random access memory cell includes a current mode latch (68) for storing two logic states and interface circuits for interfacing the input of the latch (68) with multiple input ports and the output of the latch (68) with multiple output ports. The interface circuitry comprises current switches (70-76) for switching current to a current source in the presence of a write select and a row select signal to override the holding current in the current mode latch. The output interface circuitry includes current sensors (78-84) for sensing the logic state in the latch and outputting it to the select output ports in the presence of a row select signal. The current switches and the current sensors utilize current mode logic and with a common current source. The current source is disable in the absence of any row select signal such that power is not drawn by the memory cell in the unselected state.