Abstract: An integrated circuit is described which includes a plurality of output transistors (T1, T2, . . . Tn) for emitting binary signals to associated output terminals (A1, A2, . . . An). The integrated circuit further includes at least one ground terminal (M; M1, M2 . . . Mn). Between the base of each transistor (T1, T2, . . . Tn) and the at least one ground terminal (M; M1, M2, . . . Mn) a current source (R1, D1) controlled by the base voltage is inserted.

Abstract: A static random access memory, wherein power consumption is reduced by using asynchronous edge-triggered power down gates to power up only elements in the critical circuit path for only as long as necessary to access the memory. Thus, power consumption in the memory is reduced to nearly an absolute minimum. This invention uses the address transition clock to provide an asynchronous power up function to various parts of the static RAM so that only the circuit which is propagating the signal is powered up and the power is held high just long enough for the signal to propagate. This is performed using intrinsic timing elements of the RAM critical path so that the timing of the signal and power cycles track each other.

Abstract: A picture processor comprising a memory array for storing video data involving at least one picture frame and a line buffer memory for processing at a high rate video signals included in one scan line of picture frame.

Abstract: A processing apparatus and method utilizing a single process chamber to deposit a layer of doped or undoped silicon dioxide utilizing a silicon source and a dopant gas and a remote plasma from an oxygen source and a source of additional ultraviolet light.

Abstract: Interleaving troughs (28-30) are securely fixed to a front cover (12) and a back cover (14) of a hinged apparatus (10). The first and second troughs (28-30) are generally semicircular in shape and are dimensioned to slidably cooperate with each other. A gap (34) is formed between the second trough (30) and the back cover (14) to receive the first trough (28) when the apparatus (10) is in a fully opened position. When the apparatus (10) is closed, first and second troughs (28-30) form a generally cylindrical container (36) for holding a wire spiral (26) of a book (20). When the apparatus (10) is closed, a void (38) of less than 3/16 inch is formed between the first and second troughs (28-30). The void (38) meets the ASTM standards for toy safety with regard to a pinching hazard.

Abstract: A speech encoding process, wherein a first sequence of input data representative of a written version of a message to be coded is encoded to provide a first encoded speech sequence corresponding to the written version of the message to be coded, and a second sequence of input data derived from speech defining a spoken version of the same message is analyzed by a linear predictive codeing analyzer and encoding circuit to provide a second encoded speech sequence corresponding to the spoken version of the message to be coded. The codes of the corresponding written message and the codes of the spoken message are then combined in a control circuit encompassing an adaptation algorithm, and a composite encoded speech sequence is generated corresponding to the message from the combination of the first encoded speech sequence of the written version of the message and encoded intonation parameters of speech included in a portion of the second encoded speech sequence corresponding to the spoken version of the message.

Abstract: A process module which is compatible with a system using primarily vacuum wafer transport, but which permits processing multiple slices in parallel in a single module. This is accomplished by using notched quartz arms in the module, so that the transfer arm can place each of several wafers into one set of notches in the quartz arms. Optionally, a vertical degree of movement in the arm may be used to accomplish this, and the quartz arms may be immovable. This means that the port from the multi-wafer module into the wafer transfer system must be high enough to accommodate the necessary vertical movement of the transfer arm. After the transfer arm has placed the wafer on the quartz arms, the process module can be elevated to close around the set of wafers and made a seal.

Abstract: A processing apparatus and method utilizing a single process chamber for deposition of silicon nitride with a silicon source, a remote plasma including a nitrogen source, additional ultraviolet energy coupled into the process chamber to provide additional molecular excitation of the silicon source.

Abstract: Recognition of sound units is improved by comparing frame-pair feature vectors which helps compensate for context variations in the pronunciation of sound units. A plurality of reference frames are stored of reference feature vectors representing reference words. A linear predictive coder (10) generates a plurality of spectral feature vectors for each frame of the speech signals. A filter bank system (12) transforms the spectral feature vectors to filter bank representations. A principal feature vector transformer (14) transforms the filter bank representations to an identity matrix of transformed input feature vectors. A concatenate frame system (16) concatenates the input feature vectors of adjacent frames to form the feature vector of a frame-pair. A transformer (18) and a comparator (20) compute the likelihood that each input feature vector for a frame-pair was produced by each reference frame. This computation is performed individually and independently for each reference frame-pairs.

Abstract: A heating lamp assembly for use with semiconductor reactors has a reflector assembly constructed of tubes joined together by heat conductive spacers to provide for water cooling of the reflector assembly, has mounting pins for providing variable spacing of heating lamps, and water manifolds on each side of the reflector assembly for directing water through the cooling tubes. One or more blocking gates are mounted on the lamp mounting pins to direct cooling air flow across the heating lamps.

Abstract: An interrupt system provides interrupt signals to devices to be interrupted by indicating the presence of interrupts in a random access memory associated with each of the devices to be interrupted. The address of the interrupt signal that is written is assigned to a respective one of a plurality of addresses, each of which is assigned to a respective one of a plurality of interrupting devices and is indicative of the priority of the interrupt. The controller associated with each of the devices to be interrupted causes a scan of the associated memory and when an interrupt is detected, the address of the interrupt is sent to the interrupted device. The interrupted device then recognizes the interrupt by reason of its address and performs the appropriate interrupt routine. When an interrupt is written into the memory, a comparison is made of the address of the newly written interrupt with the address of the last scanned position.

Abstract: A processing apparatus and method for performing a descum process (i.e. a process for removal of polymers and other organic residues) which uses a remote plasma, supplied through a distributor which includes a two-stage showerhead, to achieve improved results.

Abstract: The mode of operation of an intergrated circuit capable of several modes of operation is determined by at least one signal applied to one or more mode selection terminal pins. The signal applied is a selected one of at least two signals derived from a clock signal used by the integrated circuit in its operation. The clock signal is generated by an oscillator which may be included in the integrated circuit or external to it; in either case, the clock signal appears at another terminal pin of the integrated circuit.

Abstract: A semiconductor device is primarily composed of a semiconductor substrate of a first conductivity type and a semidonductor layer of a second conductivity type formed in a principal plane of the semiconductor substrate. The device has both a bipolar transistor with the semiconductor layer itself being the collector region. The base region is of the first conductivity type and the emitter region is of the second conductivity type. Both regions are formed in the same layer as a JFET struture which includes the above collector region as channel a and the above base region as a gate. A semiconductor region of the first conductivity type is formed in the above semiconductor layer, the semiconductor layer itself, and the above base and emitter regions constitute a thyristor structure.

Abstract: An apparatus for storing a plurality of articles each having a surface portion and conveying each of the articles to a desired position outside the apparatus, including a storage assembly for storing the articles so that the articles are positioned each with its surface portion spaced apart from another article to form a gap between every adjacent two of the articles, and a transfer assembly for conveying each of the articles to the desired position outside the apparatus, characterized by a fetch mechanism intervening in effect between the storage assembly and the transfer assembly and operative to move a selected one of the articles from the storage assembly to a predetermined position with respect to the transfer assembly.

Abstract: A film for hermetically passivating monocrystalline silicon includes sequential layers of undoped amorphous silicon, oxygen doped polycrystalline silicon, silicon rich oxynitride, and silicon nitride, and may be overlaid with an organic bulk dielectric such as polyimide. The inorganic film accurately sets the monocrystalline surface Fermi potential, independent of ambient electrical, mechanical, thermal, ionic, and moisture conditions. A method for depositing the amorphous silicon and the oxygen doped polycrystalline silicon layers of the film includes sequentially reacting monosilane in an inert carrier gas, such as helium or argon, and nitrous oxide. The layers are blended by varying the deposition temperature, the nitrous oxide flow rate, the monosilane flow rate, the monosilane dilution, and the inert carrier gas species. The layers are annealed to locally segregate the oxygen, to grow the grains to the proper size, and to set the final recombination velocity of the monocrystalline region.

Abstract: A video information editing system has a field memory portion capable of storing predetermined units of digital video information, a peripheral circuit portion to make this field memory portion operate, and a video data writing circuit to rewrite video information from the field memory portion, these being added to a known video information reproducing device in the form of a video tape recorder/playback device. The system is so constructed as to access only specific video information comprising a portion of the complete original video information contained on the recording tape of the video tape recorder/playback device.

Abstract: A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a buried perimeter (92) of the metal layer (62). A conductive lead (86) is formed in the Schottky via (68). A poly emitter terminal (46) connects a small sized emitter (50) formed in an epitaxial region (24) to the exterior. Poly emitter (46) presents a large area (76) to the exterior for alignment with a via (66) through a passivating dielectric layer (64), thus alleviating alignment problems.

Abstract: A semiconductor memory system using address signals each consisting of a first predetermined number of logic bits, comprising a memory array having a number of memory cells and access lines along which the memory cells are arranged in rows or columns, and a programmable address decoder responsive to a second number of logic bits of each of the address signals, the second predetermined number being not larger than the first predetermined number. The address decoder comprises a plurality of address generation networks commonly connected to the address bus and respectively associated with the access lines and is operative to generate a predetermined sequence of address bits representing a desired address for one of the access lines in the memory array in response to the second predetermined number of address bits of each of the address signals.

Abstract: A dual port random access memory assembly having a custom tailored variable organization comprising a memory array or core (matrix) having, besides a pin for the supply voltage (VDD) connection and a pin for the ground voltage (GND) connection, a first and a second port, each port having two pins for supplying the control signals enabling the read and write operations, respectively; a set of pins for application of the address signals and a set of n data input/output (I/O) pins; wherein an organizer circuit is interposed between the n data input/output pins of the port which is to be organized or formatted and the memory array, which organizer circuit is driven by a number m of signals derived from a corresponding number m of data input/output pins of the output port and applied thereto through a corresponding number m of electronic switches and a corresponding number m of sharper circuits, so as to enable variable sets of bits to access to the memory through selective selts of input terminals and to convert