Abstract: A driver circuit provides a high output current at a fast slew rate to a low impedance load. The driver circuit has an output circuit including a first bipolar transistor having a collector emitter path between a voltage supply line and a node for connection to a load. The output circuit also includes a first FET having its source-drain path connected between the voltage supply line and the base of the bipolar transistor, and its gate connected to an input node. An additional circuit supplies drive current to the base of the first bipolar transistor only to assist the first bipolar transistor turn-on, so that the additional circuit does not add extra voltage drop across the first bipolar transistor during turned on operation. In one embodiment, the first and second bipolar transistors are NPN transistors, and the first and second FETs are p-channel FET devices.

Abstract: A Class A amplifier has a balanced input circuit including first and second input transistors to receive inverting and non-inverting inputs and to provide an output signal on the collector of the first input transistor. First and second load transistors are associated with the input transistors, the bases of the load transistors being connected to the collector of the second input transistor. An output circuit has source and sink output NPN transistors connected to receive the output signal from the first input transistor, and a circuit is provided for dynamically biasing at least one sink output transistor to have a minimum biasing current in a quiescent state, and increased biasing current in a current sink state. The circuit for dynamically biasing the output transistors has a pair of bias NPN transistors with their collector-emitter paths connected in series, and with the base of one connected to receive the output of the first input transistor.

Abstract: Voltage slew-rate control for inductive load connected to the drain of an insulated gate enhancement mode field effect transistor is disclosed. The voltage slew-rate control is accomplished by incorporating a current integrator between the gate and drain of the field effect transistor, thereby effectively annihilating the capacitance of the field effect transistor which has heretofore proven to be generally responsible for instability and oscillations when slew-rate control is attempted in such a circuit. The current integrator includes a capacitor and a current source in circuit with a high speed unity gain buffer amplifier. The buffer amplifier preferably has a low impedance through the frequencies of interest to prevent the natural resonances of stray capacitances with the inductive load.

Abstract: A circuit for presenting a multiplied impedance at in input node includes a resistor having a value desired to be multiplied at the input node connected at one end to a reference potential. A first transistor has a current path in series between the input node and the other end of the resistor. A voltage divider is connected at one end to the reference potential, and a second transistor has a current path in series between a voltage source and the other end of the voltage divider, so that the second transistor and the voltage divider form an emitter follower circuit, to provide feedback to said first transistor circuit. A current control element of the first transistor is connected to receive the divided voltage from the voltage divider, and a current control element of the second transistor being connected to the input node. The transistors can be either bipolar, enhancement FET or MOS enhancement FET type devices.

Abstract: A method for forming a contact in a semiconductor integrated circuit includes the formation of a conformal oxide layer over the device followed by formation of a doped glass layer. The integrated circuit is heated to cause the glass layer to reflow, improving planarity of the circuit. A second conformal oxide layer is then formed, and contact vias are cut through the three part interlevel dielectric layer. Side walls are then formed in the via by depositing a third conformal layer, and anisotropically etching such layer. This isolates the doped reflowable glass layer from the via. Metal interconnect can then be deposited and defined, forming a contact in the via.

Abstract: An N.sup.+ buried layer is formed under all the N-channel devices in the memory array of an integrated circuit device. The N.sup.+ buried layer can also be formed under N-channel input/output devices. The N.sup.+ buried layers include contacts to the power supply. Such a device layout provides for complete isolation of the memory array from the remainder of the circuitry. The isolation of the N-channel input/output devices also provides for enhanced immunity to input/output noise.

Abstract: A logic output macrocell (30) is programmable to select between a registered output (38a-n) or a nonregistered output (42a-n). The selection between the two outputs can be either reversible through coupling to a selecting output (58) of a combinatorial logic matrix (12) or it can be permanently programmed with the aid of an architectural fuse (52a-n).

Abstract: The device refreshes the cells of an array of dynamic memory cells a row at a time during precharging of the bit or column lines. Normal access to read or write to the cells also refreshes them. Refresh circuits connect to the row line between the row address decoder and the cells, and include shift register stages connected to the row lines. A bit of one sense shifting through the stages indicates the row to be refreshed and a refresh signal connected to the stages times the refresh during the precharge. Using multiple, sequential refresh signals refreshes alternating rows of the cells.

Abstract: A process is disclosed for making a conductive interconnecting path formed between two conductive areas of an integrated circuit, the conductive areas separated by at least an insulating layer of silicon nitride over a layer of oxide. The interconnecting path is formed by depositing a thick insulator coating, over the conductive and non-conductive areas then forming a vertical-walled trench, with said silicon nitride acting as an etch stop, in the thick insulator between conducting areas, then filling the trench with conductive material using chemical vapor deposition, and finally removing conductive material except for that conductive material deposited in the trench.

Abstract: A sense amplifier for a read only memory cell array which includes a dynamic NOR circuit having high impedance inputs coupled to bitlines of the array. An inverter circuit has an input coupled to an output of the dynamic NOR circuit. An output buffer circuit has an input coupled to an output of the inverter circuit.

Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. A thin layer of titanium or the like is deposited, extending into a contact hole, then polysilicon is deposited over the titanium coating the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create a titanium silicide layer, including conductive sidewalls or a plug. Metal contacts and interconnections then engage the direct-reacted silicide rather than relying upon step coverage.

Abstract: A semiconductor device is programmed by a laser beam which causes an insulator between two conductors on a silicon substrate to be permanently altered, as by breakdown of the insulator. The conductors may be metals such as aluminum or tungsten, and the insulator is a layer of deposited or thermal silicon oxide. The breakdown may be enhanced by voltage applied between the conductors while the laser beam is focused on the structure.

Abstract: The specification discloses a transition speed up circuit including an input transistor (14) for receiving a variable input voltage. An output transistor (16) is connected to the input transistor (14) to receive turn on current. A first diode (32) is connected at its cathode to the collector of the input transistor (14). A resistor (46) is connected between the anode of diode (32) and the output terminal (18). A speed up transistor (42) is connected at its emitter to the collector of input transistor (14) to supply speed up current through input transistor (14) to output transistor (16). A second diode (44) is connected between the base of speed up transistor (42) and the junction of first diode (32) and resistor (46). The speed up current terminates when the voltage at the output terminal (18) falls to a level determined by the value of resistor (46).

Abstract: An article holder characterizd by a unitary construction forming a living hinge structure provided by integral sheet portions and sections coupled together across hinge lines to provide ease of mounting an article on and removing the article from the holder and to permit significant reduction in the number of the component members and elements and accordingly the production cost of the article holder.

Abstract: A dual dielectric gate system utilizes a dual dielectric system with a first silicon dioxide dielectric film or layer at the monocrystalline substrate surface, or termination. The substrate is of silicon optionally counterdoped with germanium. The dual dielectric system includes a dielectric film at the substrate surface of thicknesses of from 200.ANG. to 1000.ANG. (or greater). A layer of undoped amorphous silicon and a second layer of silicon dioxide, respectively overlie the first layer silicon dioxide, and an aluminum gate metal layer overlies the second silicon dioxide layer. The structure can be patterned by selectively patterning photoresist and a dry or a dry/wet etch processes. The structure is patterned and etched as desired.

Abstract: A semiconductor device fabrication process comprising the following sequential steps:Sequential formation of an oxide layer and first layer of masking material resistant both to oxidation (particularly preventing the action of oxidants, such as water vapors and O.sub.

Abstract: A unital casing structure of a portable electronic appliance such as a handheld or desktop calculator, comprising at least two panel sections having a straight boundary line therebetween and integrally coupled together across the boundary line whereby the panel sections are foldable with respect to each other about an axis extending along the boundary line between the panel sections so that the two panel sections are coupled together in a face-to-face relationship. The casing structure may further comprise an intermediate panel section bridging the two panel sections, the intermediate panel section being angularly movable with respect to the two panel sections about two axes parallel with and spaced apart across the boundary line between the panel section and being foldable with respect to each of the two panel sections about each of the two axes.

Abstract: Method for cleaning material from the outer edge of an object by applying a solvent for the material to a flat surface adjacent the edge and moving the solvent onto the edge by centrifugal force.

Abstract: A CCD imager of small geometry which has increased well capacity. An additional p-type implant 112 selectively located creates a p-type region 112 below the channel region 13 of the virtual well regions 34, which increases the capacitance in the virtual well regions 34.

Abstract: A CCD imager wherein a mixed MOSFET and JFET periphery is provided using the same device doping profiles as are used for fabrication of the CCD structure. This provides simple fabrication of low-noise amplifiers integrated with the CCD array. Preferably the gate of the JFET is formed with the same implant which forms the virtual phase electrode in an array of virtual phase CCD cells. Preferably the JFETs are used as loads in source-follower stages. Preferably the MOSFET devices include both buried-channel and surface-channel devices connected to a common drain voltage; the buried-channel devices are used for earlier stages of amplification, where they can be operated in their low-noise regime, and the surface channel used for output stages. If buried channel devices were used for the output stage, then the buried-channel devices in the prior stage would have to be biased into a high-noise regime to achieve the necessary output voltage swings.