Abstract: A semiconductor device is programmed by a laser beam which causes an electrical short between two conductors on a silicon substrate, as by melting an insulator between the conductors and fusing or shorting the conductors. The conductors may be first and second levels of polycrystalline silicon in a standard double-level poly process, and the insulator is thermal silicon oxide. The laser beam is focused on an area which is shielded from the silicon substrate by the first-level conductor, so heating and disruption of the substrate or underlying circuit structure is minimized.

Abstract: A CCD imager with a correlated clamp sample and hold amplifier on chip includes a chain of CCD wells, a charge-sensing node coupled to one end of the chain of CCD wells, and a clock to clock charge packets from the chain of CCD wells into the charge-sensing node. A dummy charge-sensing node is integrated into the same monocrystalline semiconductor substrate as the charge-sensing node, and the charge-sensing node and the dummy node are connected to a common reference voltage. An amplifier senses a predetermined voltage change on the charge-sensing node with reference to the voltage on the dummy node after a charge packet has been transferred into the charge-sensing node.

Abstract: A semiconductor Hall effect device having a stable and more controllable offset voltage is formed, in one embodiment, of an N-type silicon epitaxial layer overlying a P-type silicon substrate, and a P+-type region is formed, for example, by ion implantation, in the surface of the epitaxial layer over the active area of the Hall element. The P+-type region effectively shields the surface of the Hall element to prevent induced surface potential variations. Current and voltage sense contacts are provided by N+-type regions which penetrate through the P+-type shield region to contact the N-type epitaxial layer.

Abstract: A logic unit used as the basic building block in a bipolar integrated circuit is formed in a rectangular oxide-isolated island wherein thick oxide walls at one end of the island define three of four edges of a P-type region which serves both as the base of an NPN drive transistor and the emitter of a PNP clamp transistor. An input contact to the logic unit is disposed on the upper semiconductor surface of the island in ohmic contact with the common P-type region. The input contact extends across the entire width of the island to minimize the base resistance of the drive transistor and thus increase the switching speed of the logic unit.

Abstract: A color CCD imager with three correlated clamp-sample-and-hold sense amplifiers (one for each color channel). The three control lines necessary to operate this type of amplifier, together with the clock lines necessary for the three shift registers which feed them, are all wired together, so that correct phasing of the three outputs is maintained with only three clock lines.

Abstract: An oscillator for an integrated circuit which includes a Schmitt trigger having an upper threshold voltage V.sub.H and a lower threshold voltage V.sub.L, a capacitor coupled between an input to the trigger and ground, a current generator coupled to the trigger input for charging the capacitor at a constant rate and a current generator coupled to the trigger input for discharging the capacitor at a constant rate. A charge switch in series with the charging current generator reversibly couples the charging current generator between a source of high voltage and the trigger input in response to a change in state of the trigger from a first state to a second state. A discharge switch in series with the discharging current generator reversibly couples the latter across the capacitor in response to a change in state of the trigger from the second state to the first state.

Abstract: A CCD imager having one or more serial output shift registers 16, wherein the dark reference area 10 prime at the edge of the image area 10 is located so that it will be clocked into the opposite end 16 prime of the serial shift register 16 from the output amplifier 18. After a line of image information is clocked through the output amplifier 18, the dark reference information is left in dummy pixel area 16 double prime. At the next line transfer, the dark reference information stored in the portion 16 double prime is the first clocked into the output amplifier 18, and thus provides the reference information.Standard TV formats have a limited amount of time available for horizontal blanking; this time limit, together with the CCD well clock rate, restricts the number of CCD wells which can separate the amplifier from the edge of the array.

Abstract: A two-lead Hall effect sensor (10) has a combined voltage supply and output terminal (12) and a ground or reference terminal (14). A Hall device (16), a comparator (18) and a voltage/current converter (20) are each connected between terminals (12) and (14). Hall device (16) supplies a first signal to comparator (18) when it senses a magnetic field strength above a predetermined amount, and supplies a second signal in the absence of the magnetic field strength. Comparator (18) in turn supplies either a first voltage state or a second voltage state to the converter (20). Converter (20) converts the first voltage state into a first current appearing at terminal (12), indicating the sensing of a magnetic field, and similarly converts the second voltage state to a second current, indicating a weak or absent magnetic field.

Abstract: Molybdenum-gate transistors with self-aligned, silicided source/drain regions are made by a process that avoids unwanted etching of the molybdenum of the gate when the unreacted metal used for siliciding is removed. The molybdenum gate is protected by encapsulating with a cap oxide and sidewall oxide; this encapsulation is applied in a manner to seal the interfaces between the two oxides. The oxides may be dual layer--first plasma deposited then phosphorus doped CVD oxide. A dilute sulphuric acid etch may be used to remove unreacted titanium employed for the siliciding.

Abstract: A sensor (10) responding to the action a force comprises a base body (12) and a force takeup element (14) which is connected to the base body (12) via at least one support element (16, 18, 20, 22). The support element deforms under the influence of a force acting on the takeup element (14). In the deformation region between each support element (16, 18, 20, 22) and the force takeup element (14) a measuring member (32, 34, 36, 38) is disposed which reacts to the deformation with a change in a physical parameter. An uninterrupted conductor path (44) is provided which extends from a first terminal land (46) on the base body (12) via each support element (16, 18, 20, 22) and the force takeup element (14) to a second terminal land (48) on the base body (12).

Abstract: In accordance with a broad aspect of the invention, a system is presented for parametrically and functionally testing integrated circuit devices in parallel. At least one integrated circuit device receiving channel is provided for defining a plurality of integrated circuit device test stations therealong, and means are provided for delivering parametric and functional test signals at least functionally in parallel to each of the integrated circuit device test stations. Means are provided at each test station for selectively engaging the integrated circuit devices to apply the parametric and functional test signals to the integrated circuit device at that station, and to selectively isolate the device from the test signals. Means are provided for receiving an output from each test location in response to the test signals, and means for determining from the output the parameters of each tested integrated circuit device.

Abstract: A transport mechanism (40) for transporting a semiconductor slice cassette between a clean carrier (10) and a process machine comprises a housing (41) having a forward portion (42) positioned in the people-occupied area of the clean room and a rear portion (46) positioned in the process machine area aerodynamically isolated from people. A moveable glider plate (50) is adapted to receive the carrier (10) and is initially positioned in an aperture provided in the upper surface of forward portion (42). A gearing mechanism (54) is provided which cooperates with glider plate (50) to move the semiconductor slice cassettes mounted on the base of carrier (10) between forward portion (42) and rear portion (46).

Abstract: Full oxide isolation of epitaxial islands can be accomplished by oxidizing suitably porous silicon. The porous silicon can be created by anodizing highly doped n+ silicon in hydroflouric acid. Lesser doped epitaxial regions will not become porous and will become isolated islands suitable for the fabrication of semiconductor devices.

Abstract: A clamp circuit which breaks down under application of high voltage is connected to an input pin to be protected through a unidirectional device such as a diode. A voltage supply is connected to the discharge path between the unidirectional device and the clamp. The voltage supply will therefore supply any leakage currents which may be drawn by the clamp during normal operation.

Abstract: An improved differential amplifier having improved immunity to signals on the power supply terminals (32,34) thereof. The low impedance path between the power supply terminals (32,34) of the amplifier and the second gain stage transistor (24) is removed and connected to a low noise reference. The source of the transistor (24) is provided as an output terminal (23) of the amplifier and can be optionally connected to any low noise reference. High impedance input current mirrors (47,55,63,67) are connected between the supply voltage rails (33,35) and the amplifier, thereby further reducing the amplifier's susceptibility to noise.

Abstract: A test signal, used to initialize an integrated circuit chip for testing, is multiplexed with a data input line of the chip. The test signal circuitry is inactivated during normal operation of the chip. The test circuitry is activated only when a special input signal, which is a voltage at some midpoint between logic states, is applied to the data input.

Abstract: A portable carrier (10) for storage and transportation of semiconductor slice cassettes in a clean room environment which shields the semiconductor slices from VLF air in people occupied areas includes a base (12), a pair of spring-mounted cradles (14) mounted on base (12) for supporting the semiconductor slice cassette and a cover (16) for disposal on base (12) to provide a sealed volume. Carrier (10) also includes a latch (20) for removably coupling cover (16) onto base (12). Latch (20) includes a handle (22) at the terminal end thereof to facilitate handling and transporting of carrier (10) when cover (16) is locked in place on base (12). A latch tube (24) is mounted proximate the center of base (12) and cooperates with latch (20) to couple cover (16) onto base (12).

Abstract: A current switch whose turn-on and turn-off voltages are independent of temperature includes a transistor switch circuit having two input transistors to which a differential voltage is applied, two sensing transistors for sensing turn-on and turn-off voltages respectively, and an output transistor controlled by the sensing transistors. A differential voltage sensing circuit including a differential transistor pair is connected to receive the differential voltage at the inputs of the transistors and to deliver the differential voltage to the transistor switch circuit. A biasing current source is provided to supply biasing currents which vary as a function of temperature to the input and sensing transistors of the switch circuit, and a biasing current source is provided to supply a biasing current which varies as a function of temperature squared to the differential transistor pair.