Abstract: A power amplifier has a signal input stage to which an input signal is applied to produce an input stage output. An input signal amplifier is connected to receive the input signal to produce an amplified input signal from an active device at an output of the input signal amplifier. A push-pull signal output stage has first and second transistors. The first transistor has a current path connected between a supply voltage and an output node, and the second transistor has a current path connected between a reference voltage and the output node. The amplifier output provides variable drive current directly to a base of the first transistor, thereby enabling increased drive current to be realized. The power amplifier also includes a common mode biasing circuit connected to bias the first and second transistors for class AB operation, and the input stage output provides a signal base drive current to the first transistor separate from the common mode biasing circuit.

Abstract: A circuit and a method for filtering the ripple in an output of a multi-phase alternator in a vehicle system having a regulating circuit that regulates the output of the alternator includes a switch connected in series between a system voltage and the input of the regulating circuit, and circuitry for closing the switch at a predetermined phase of the voltage of at least one of the stator windings of the alternator. The circuitry for closing the switch operates to close the switch at a conduction switchover point among the stator windings in synchronism with a voltage waveform of the at least one of the stator windings, and is timed to produce an aliased waveform for application to the regulator. The output of the switch is applied to an integrator for integrating the output voltage from the alternator during an entire time cycle period of one of the windings of the stator coils for application to the regulator.

Abstract: A circuit for initializing the output voltage of an analog circuit includes a switch operative to connect an input of the analog circuit to a first reference potential during an initializing period. A comparator is connected to compare the output voltage of the analog circuit with a second reference potential to produce an output representing the comparison. A resistor ladder having a plurality of voltage step output lines along its length is connected to inputs of a multiplexer, the multiplexer having an output connected to bias the analog circuit. A counter having a clock input and a count output is connected with the count output connected to operate the multiplexer to sequentially select among the steps of the resistor ladder. A circuit clocks the counter until the output of the comparator reaches a predetermined value, wherein a voltage step output line of the resistor ladder is selected to control the output of the multiplexer.

Abstract: A circuit for providing drive current to a coil of a motor uses a sensefet current sensing device having a sense node and a source node. The source node is connected to deliver current to the coil, wherein a "sense" current proportional to said delivered current is produced on the sense node. An amplifier is connected to sense a voltage between said sense and source nodes to produce an output voltage to force a voltage on the sense node to be the same as a voltage on the source node. A pass element is connected to route said "sense" current to an output node. The circuit produces an output that is suitable for use as a feedback signal in a motor control system.

Abstract: A content addressable memory has a plurality of entry locations. Each entry location includes a comparison field and an action field. Comparitors are provided for each entry location, so that an input provided to the memory is compared simultaneously to the comparison fields of every entry. The action fields of all entries which match the input value are combined to generate a single output value. Each entry includes a bit which indicates whether such entry is to be deleted when a match occurs with an input value. Each entry in the memory can be assigned an arbitrary label for use in direct accessing by a central processor unit.

Abstract: A method for aligning a rotor of a brushless and sensorless DC motor, the motor having a stator with at least two coils, sets of the coils being selectively energizable by a power source connected to the motor, includes steps of energizing a first set of at least one coil of the at least two coils; generating a signal indicating whether the rotor has been rotated at a rotary speed greater than a predetermined rotary speed while the first set was energized; and when the signal indicates that the rotor has not been rotated at a rotary speed greater than the predetermined rotary speed, switching the connection between the power source and the motor and energizing a second set of at least one coil of the at least two coils.

Abstract: A method for planarizing an integrated circuit structure having a glass layer overlying an oxide layer of an integrated circuit is presented. The method includes the steps of selectively etching portions of the glass structure that overlie portions of the oxide layer that have higher elevations than other portions of the oxide layer, and then etching the glass layer overall. The etching step includes forming a layer of photoresist over the glass layer, exposing selected areas of the photoresist over the portions of the oxide layer that have higher elevations than other portions of the oxide layer, removing the exposed areas of the photoresist, and etching the glass layer within the removed areas of the photoresist. The mask used in patterning the photoresist can be the same mask, or its negative, that is used in forming the metalization layer over which the oxide and glass layers have been formed.

Abstract: An operational amplifier input stage has at least two positive input transistors and one negative input transistor for providing more accurate and efficient limiting or rectification in limiter and rectifier circuits. The two positive input transistors are connected in parallel having a common drain connected to one side of a load and the negative input transistor's drain is connected to the other side of the load. The sources of all transistors are connected to a common node which is connected to a constant current source. This arrangement enables simplistic high accuracy limiting and rectifier circuits, having a reduced number of extrinsic components, thereby reducing unwanted speed limitations, to be realized. The operational amplifier input stage is also very useful in low supply circuit applications.

Abstract: A full wave rectifier includes an amplifier having a minus input, a plus input and an amplifier output; an input resistor connected between a circuit input and the minus input; and a current bridge having an output terminal connected to the circuit output, a first terminal connected to the minus input and a second terminal connected to the amplifier output. The current bridge includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit includes a first current source and a second current source, a source end of each current source of the first and second current sources being connected to the first terminal, a drain end of the first current source being connected to the second terminal and a drain end of the second current source being connected to the output terminal.

Abstract: A digital processing circuit and method includes a signal modulator connected to modulate a delta-modulated first input signal with a digital second input signal to produce a delta modulated output pulse stream. The digital output can be directly used for many purposes, or the digital output can be demodulated to produce an analog output signal using a low pass filter. Also, if desired, the delta modulated pulse first pulse stream can be generated from an analog signal input through use of a sigma-delta modulator. The signal modulator includes a plurality of switches, each operated by a respective bit of the digital second input signal to switch between the delta modulated first input signal and a known pulse sequence, such as an idle sequence, for delivery to a switch output. A plurality of adder circuits are connected in series to add the successive outputs of the plurality of switches to the delta modulated pulse first input signal to produce the delta modulated output pulse stream.

Abstract: A circuit for controlling a current in a load that includes an inductive component provides a high constant gain at low frequencies, a gain roll off at medium frequencies, and a low gain above unity gain at frequencies between the medium frequencies to high frequencies so that the gain roll off of the circuit to below unity gain is provided by a pole of the inductive load component. As a result, the circuit has a bandwidth limited only by the poles of the load. The circuit has a high gain amplifier with an input connected to receive a input control signal, and a low gain amplifier with an output connected to a control element of a switching element in a current path of the load. A frequency compensation circuit is connected between an output of the high gain amplifier and an input of the low gain amplifier, and includes a high frequency current bypass path and a resistor in series therewith operative to reduce the signal input to the low gain amplifier at high frequencies.

Abstract: A circuit and method for operating a polyphase dc motor of the type having a plurality of driving coils that are commutatively energized in a predetermined sequence to rotate a rotor has a zero crossing detector connected to determine when a back emf of a floating driving coil crosses zero. A generator for generating commutation sequence signals controls which of said driving coils are energized a delayed time after said zero crossing detector detects that a back emf of a floating driving coil has crossed zero. A mask circuit inhibits said zero crossing detector for a delayed time after a commutation change, in dependence upon an acceleration of the rotor. Also, a circuit is provided for adjusting the commutation delay time after a back emf of a floating one of said coils crosses zero, in dependence upon the acceleration of the rotor.

Abstract: Pulse Width Modulation (PWM) techniques, often used to reduce the power dissipation in polyphase motors, chop the current in the coils of the motor at their peak current levels, to achieve maximum torque, to allow rapid accelerations, and to reduce the power dissipated in the chip to a level proportional to the duty cycle. During the time the current is switched off, the current which has been established in the coils of the motor is allowed to be dissipated. Accordingly, when the switching transistors of the active coils are turned off during PWM mode chopping, a non-rectifying ground return path is provided for flyback energy in the active driving coil. This non-rectifying ground return path is provided by switching transistors in parallel with flyback diodes, operated in a form of synchronous rectification. This gives an alternate current path for the coil current to reduce the voltage drop across the diodes, and thereby reduce the power dissipation and heat in the chip.

Abstract: A circuit for operating a polyphase dc motor, for example of the type having a plurality of "Y" connected stator coils, has circuitry for unambiguously determining the actual instantaneous position of the rotor of the motor, circuitry for determining a desired rotor position precedent to executing a desired commutation sequence, and circuitry for executing the desired commutation sequence when the circuit for determining the actual instantaneous position of the rotor detects that the rotor is actually in the desired rotor position. The circuitry for unambiguously determining the actual instantaneous position of the rotor includes a back emf amplifier switchably connected to at least one floating coil, and circuitry for determining when the voltage received by the back emf amplifier crosses a reference voltage from a predetermined direction.

Abstract: A driver circuit for providing drive current to a coil for positioning a read/write head of a memory disk system and method are presented. The driver circuit includes a pair of high side driver transistors having current paths connected between respective terminals of the coil and a voltage source, a first pair of low side driver transistors having current paths connected between respective terminals of the coil and a first voltage sense node, and a second pair of low side driver transistors having current paths connected between respective terminals of the coil and a second voltage sense node. A first sense resistor is connected between the first and second voltage sense nodes, and a second sense resistor is connected between the second sense node and a reference potential.

Abstract: A circuit and method for converting a digital number to an analog output signal, wherein the most significant bit or "sign" bit of the digital number is used for switching the accumulated currents of the other data bits to a chain of operational amplifiers employing feedback resistors for conversion into an output voltage of magnitude and sign corresponding to the input digital number. A decoding circuit and method enables the circuit to present an output voltage corresponding to the two's--complement of the input digital number.

Abstract: An operational amplifier having a differential signal input and an output has an input stage comprising a differential amplifier having a differential signal input and a differential signal output. The differential amplifier includes a first pair of transistors of opposite conductivity type having control elements connected to receive one side of the differential signal input, and second and third pairs of transistors of opposite conductivity type having control elements connected to receive another side of the differential signal input. The differential output of the differential amplifier is developed by outputs of the second and third pairs of transistors. A high-swing output section is connected to receive the differential signal output directly from the input stage.

Abstract: A circuit for operating a polyphase dc motor includes first circuitry for determining when the back emf of the floating driving coils crosses zero. A first counter counts a time period between a first set of zero crossings, and a second counter is loaded with the count reached by the first counter. The second counter counts a time period between a subsequently occurring set of zero crossings. If the second counter reaches zero before the occurrence of a third zero crossing, a warning signal is generated. A method for determining if a deceleration rate of a polyphase dc motor exceeds a predetermined threshold includes measuring a first period between a first set of zero crossings of the back emf of the floating driving coils, and comparing the measurement of the first period with a subsequent period between a subsequent set of zero crossings. If the subsequent period is larger than the first period by a predetermined amount a warning signal is produced.

Abstract: A stable reference voltage generator using a current mirror circuit comprising a primary branch and a secondary branch, is shown and described. A first bipolar transistor (Q1) has its collector connected in series with the primary branch of the current mirror, and a voltage divider bridge comprising at least two series-connected resistors (R1, R2), is connected in series between the secondary branch of the current mirror and the collector of a second bipolar transistor (Q2). The base of the second transistor (Q2) is connected to the common point of the series resistors, the base of the first transistor (Q1) is connected to the collector of the second transistor (Q2), and the output of the generator (V.sub.REF) is connected to the terminal of the bridge opposite that connected to the collector of the second transistor (Q.sub.2). The geometry of said transistors being such that the first transistor (Q1) is equivalent to "N" transistors identical to the second transistor (Q2) connected in parallel.