Abstract: A computer system and method of operation are disclosed that simplifies the menu bar for use by a group of active applications. The computer system typically uses a bus coupled to a central processing unit and further coupled via the bus to a computer system memory. The computer system further includes an X Window menu manager and an X Window menu bar, both of which are located within the computer system memory during operation. The X Window menu manager includes a shared menu library. The X Window menu manager implements simultaneously instantiation of a set of menu widgets from the shared menu library that are associated with a computer program selected from the several active computer programs when the program focus is shifted to one of the active programs.

Abstract: A method and system for providing a single access point for the resources of application programs distributed within a network. The single access point is provided via a master object comprising an application identification list and a plurality of application procedure interfaces. Each of the application programs has an associated agent for managing the resources of the associated application program. These agents manage the resources using a subset of the plurality of application procedure interfaces of the master object. The application identification list of the master object is used for storing the binding handle of the agent as well as the identification for the associated application. A client or user accesses the resources of a particular application program by specifying the identification of the application program and the required action to be taken by the application program to the master object.

Abstract: A system and method are provided wherein a user of an interconnected computer system can identify a specific piece of data and then access this data from another computer in the network. This is extremely useful since it is often desirable for data to be capable of being displayed and manipulated from another system during meetings, discussions and the like. The user who wishes to transfer a file to another system simply points an untethered stylus to a representation of a file, such as a filename, icon, or the like and then selects the file to be transferred. The user then carries the stylus to a remote interconnected computer and points the stylus at the remote computer which verifies the identity of the stylus and obtains a path to the selected file. The data file is then transferred from the user's computer to the remote computer through the network.

Abstract: A computer system, memory, and computer-implemented method for generating at least one high performance communication path is provided. The communication path has a plurality of linked components, including a negotiator and a controller. The method includes the steps of registering the negotiator with the controller (e.g. stream head), verifying acknowledgement of negotiation from each component linked between the negotiator and the controller, and in response to a valid verification, redirecting I/O between the controller and the negotiator.

Abstract: A method prevents a livelock condition from occurring between a host bus bridge (e.g., memory controller) and a PCI bus bridge, where the host bus bridge and PCI bus bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Specification 2.0. The method includes the first step of masking from the PCI bridge a request generated by a device on a second bus. The second step includes requesting that the host bus bridge flush all existing I/O requests and postpone any future I/O requests from a central processing unit. The third step includes, in response to a notification from the host bus bridge that all I/O requests have been flushed and that any future I/O requests from the central processing unit will be postponed, unmasking the request to the PCI bridge. The fourth step includes, in response to unmasking the request to the PCI bus bridge, granting access of the second bus from the PCI bus bridge to the device.

Abstract: A method and system for memory management and address translation mapping of pools of logical partitions for BAT and TLB entries in a data processing system is provided. An entry in an address translation buffer is created that is associated with a particular block of virtual memory comprised of a plurality of logical partitions that are grouped in one or more pools of logical partitions, wherein the size of each pool of logical partitions is equal to a preselected page size for real memory, and wherein the entry maps each pool of logical partitions to a page of real memory within a sector of real memory, wherein the size of the sector is a function of the size of the associated block of virtual memory.

Abstract: A uniquely programmed computer system, computer-implemented method, and computer readable memory embodying computer-readable detailed logic (i.e., computer readable program code) direct a computer system to display an image map having graphical objects thereon and an original appearance. At least a first portion of the graphical objects are links to other documents. The method includes the step of changing the original appearance of the first portion of the graphical objects to indicate that those graphical objects are links. This step is performed in response to user controls (e.g., a user positioning a mouse cursor) positioned on the image map.

Abstract: An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary depending on the number of execution units which are to be supported.

Abstract: A method, apparatus, and article of manufacture direct a computer system to postpone transferring focus to a newly opened window displayed on the computer display. The method includes the first step of in response to a command from user controls to open a new window, determining if an existing open window retains focus. If an existing open window retains focus, the second step includes determining if at least one key stroke has been received from a buffer while focus is being transferred to the new window. If the buffer is receiving at least one key stroke while focus is being transferred to the new window, the third step includes mapping the new window to the computer display while retaining focus with the existing window.

Abstract: A method prevents a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Specification 2.0. The method includes the first step of in response to at least first and second requests being substantially simultaneously received from at least first and second peripherals, determining if a state of a state machine corresponds to an assigned order of either the first peripheral or the second peripheral. The second step includes if the state does not correspond to the assigned order of the first peripheral or the second peripheral, advancing the state and repeating the first step until the state corresponds to one of the first or second peripherals. The third step includes if the state corresponds to the assigned order of either the first or second peripheral, determining if the selected request targets system memory.

Abstract: A method and apparatus for attaching heatsinks having a disproportional size relative to the electronic component to which they are attached. In general, the apparatus comprises variable-length attaching means for attaching each corner of the heatsink to the circuit card while maintaining sufficient contact with the electronic component. The variable-length attaching means includes a post and a receiving well. Both the post and receiving well include attaching means, such as threads and nuts, for attachment to the heatsink and circuit board, respectively. The variable-length attaching means accommodates height variations between parts, establishes high structural integrity after assembly, controls static and dynamic loading of the solder columns, allows for module re-work while re-using the heatsink and card, and provides adequate protection from shock, vibration, and handling.

Abstract: A method and system for address translation mapping of logical partitions for address translation buffer entries in a data processing system is provided. The method comprises receiving a logical address for a memory reference to a selected logical partition of a plurality of logical partitions of a particular block of virtual memory, wherein the block of virtual memory is divided into the plurality of logical partitions, and wherein the logical address includes a plurality of logical partition selection bits selecting the selected logical partition from among the plurality of logical partitions.

Abstract: A uniquely programmed computer system, computer-implemented method, and computer readable memory embodying computer-readable detail logic direct a computer system to provide viewing and adjustment of the default state (i.e., operation) of a desktop icon. The default state is performed when the desktop icon is dropped on a target icon. Therefore, if the default state is "copy", then the selected object icon is automatically copied to the target object icon when the selected icon is dropped on the target icon. The computer-implemented method includes the steps of determining if a visual state indicator option is "ON" and, if so, drawing the desktop icon(s) on the display in such a manner as to indicate to the user/viewer the default state of the icon.

Abstract: An apparatus and method transmit analyzed voice samples from a wireless transmitting device worn by a user to a remote voice activated data processing system having a speech recognition system stored thereon. The method includes the first step of storing voice characteristics of a user into a memory (e.g. a RAM chip) on a wireless transmitting device. The second step includes voice activating the transmitting device and speech recognition system. After the transmitting device and speech recognition system have been activated, the third step includes transmitting the voice characteristics from the memory to the speech recognition system, thereby enabling the user to verbally communicate directly with the voice activated data processing system.

Abstract: A uniquely programmed computer system and computer-implemented method direct a computer system to efficiently transmit voice. The method includes the steps of transforming voice from a user into text at a first system, converting a voice sample of the user into a set of voice characteristics stored in a voice database in a second system, and transmitting the text to the second system, whereby the second system converts the text into audio by synthesizing the voice of the user using the voice characteristics from the voice sample. The voice characteristics and text may be transmitted individually or jointly. However, if the system transmits voice characteristics individually, subsequent multiple text files are transmitted and converted at the second system using the stored voice characteristics located within the second system.

Abstract: An arbitration protocol, preferably known as data-valid extended (DVE) protocol, for determining which one of the two units within a computer system may obtain access to a common bus is described. The DVE protocol is based on a point-to-point communication between two peer units. The DVE protocol is a physical level signalling convention for controlling switch communications on bi-directional address buses and data buses in a boundary-latched synchronous environment. The DVE protocol is asymmetric, yet fair, and is designed to minimize the number of cycles spent (or latency) in accessing the address or data buses and to maximize the number useful cycles (or bandwidth) on the address buses as well as the data buses. The asymmetry of the DVE protocol reduces the number of cycles spent in arbitration to zero for any data transfer size greater than one.

Abstract: A method and system are disclosed for verifying consistency of an instruction execution order of a multiprocessor data processing system with a specified memory consistency model. Each processor within the multiprocessor data processing system executes instructions from an associated one of a number of instruction streams, which include instructions that store a number of unique values from multiple processors to a single selected address within memory. One of the unique values is loaded from the selected address to a particular processor within the data processing system. A set of valid values which may be returned by the loading step is determined according to the specified memory consistency model. By comparing the unique value with members of the set of valid values, the instruction execution order of the multiprocessor data processing system is verified. Utilizing the unique value which was returned by the load instruction, the set of valid values may then be updated.

Abstract: A library of performance monitor recordings is maintained according to pathologies. The library is indexed to provide a facility to diagnosis poorly performing data processing systems, by capturing performance statistics and comparing these statistics against known problematic statistics. Remote diagnosis can easily be provided by a user capturing a performance session, saving to a file, and transferring the file to a central facility for comparison against its pathological libraries.