Abstract: A method and system are provided which allow heterogeneous computing systems to have direct access to the same data storage areas on a shared data storage subsystem such that the method and system are transparent to the heterogeneous computing systems. The method and system achieve the foregoing via the following steps. A data storage subsystem controller queries all computing systems having direct access to the same data storage areas of a shared data storage subsystem as to the operating systems utilized by such computing systems. In response to answers received in response to the queries, the data storage subsystem controller creates and stores meta-data which associates each computing system having direct access with whatever operating system is running on each computing system having direct access.

Abstract: A method and system for speculatively sourcing data among cache memories within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. The requested data is then sourced from a secondary cache memory within the second processing unit onto a system data bus concurrently with invalidating a copy of the requested data from a primary cache within the second processing unit. During this time, the second processing unit is also pending for a combined response to return from all the processing units.

Abstract: An improved method of providing an operating system for a computer by defining an interface between the operating system and the computer's firmware. An executable file (soft ROS) is placed in a boot image so as to run, before execution of the real operating system, in response to the firmware seeking the operating system. The soft ROS includes instructions to determine whether the firmware conforms to the standardized interface. If so, then no special action is taken and control is passed to the operating system, but if the firmware is non-conforming in any manner, the soft ROS executes a firmware emulation module which provides the interface with the operating system. The firmware emulation module can provide missing dependencies of the firmware to the operating system, fix a defect in the firmware, or translate functions of the firmware to the pre-defined interface. This method isolates the operating system from firmware dependencies, making the operating system more portable.

Abstract: Cache and architectural functions within a cache controller are layered and provided with generic interfaces, isolating controller logic from specific architectural complexities. Controller logic may thus be readily duplicated to extend a nonshared cache controller design to a shared cache controller design, with only straightforward modifications required. Throttling of processor-initiated operations handled by the same controller logic resolves operation flow rate issues with acceptable performance trade-offs.

Abstract: A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the order data on a second bus having the second ordering policy. The system includes a plurality of execution units for storing operations and executing the transfer of data between the first and second buses, each one of the execution units being assigned to a group which represents a class of operations. The system also includes intra prioritizer for each group, prioritizing the word operations according to the second ordering policy exclusive of the operation stored in the other groups. The apparatus also includes inter prioritizer for determining which one of the prioritized operations can proceed to execute according to the second ordering policy.

Abstract: A method and system for translating peer-to-peer access across multiple Peripheral Component Interconnect (PCI) host bridges within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. A first and at least a second PCI local buses are also connected to the system bus via a first PCI host bridge and a second PCI host bridge, respectively. The two PCI local buses have bus transaction protocols that are different from those of the system bus. At least one PCI device is connected to each of the two PCI local buses, and shares data with the processor and the system memory. In addition, each PCI device shares data with the other PCI device as peer-to-peer devices across multiple PCI host bridges.

Abstract: A method of handling load-and-reserve instructions in a multi-processor computer system wherein the processing units have multi-level caches. Symmetric multi-processor (SMP) computers use cache coherency to ensure the same values for a given memory address are provided to all processors in the system. Load-and-reserve instructions used, for example, in quick read-and-write operations, can become unnecessarily complicated. The present invention provides a method of accessing values in the computer's memory by loading the value from the memory device into all of said caches, and sending a reserve bus operation from a higher-level cache to the next lower-level cache only when the value is to be cast out of the higher cache, and thereafter casting out the value from the higher cache after sending the reserve bus operation. This procedure is preferably used for all caches in a multi-level cache architecture, i.e.

Abstract: A method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. The requested data is then read from a cache memory within the second processing unit before a combined response from all the processing units returns to the second processing unit.

Abstract: A process and apparatus for writing an item of data to a line in a memory table shared by a plurality of processors is disclosed. The process comprises the steps of determining if the item is already in the line; if the item is not in the line, then determining if the line is empty; if the line is empty, then performing the following steps: creating a reservation for the line for a processor requesting to write the item to the line and trying to write, by the processor requesting to write the item to the line, the item to the line. Although more than one processor can hold a reservation for the line, only one processor can add an item to the line since the reservation for the line is removed or cleared in all processors when the first processor, holding a reservation for the line, writes an item to the line.

Abstract: An apparatus, method, and memory direct a computer system, having at least a processor, memory, and touchscreen device (e.g., a touchscreen or a touchpad and display device) to execute at least one action on an object and/or text. The method includes detecting at least one item (e.g., fingers, stylus) placed on the touchscreen device, counting the number of items placed on the touchscreen device, determining if an associated action corresponds to the numbers of items and, if an associated action corresponds to the number of items, executing the associated action.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requestors that share the resource. Each of the requestors is dynamically associated with a priority weight in response to events in the data processing system. The priority weight indicates a probability that the associated requestor will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requestors. In response to the current priorities of the requestors, a request for access to the resource is granted.

Abstract: A method and system for back-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, a store queue within a data-processing system includes a front-end queue and a back-end queue. A multiple of entries is provided in the back-end queue, and each entry includes an address field, a byte-count field, and a data field. A determination is first made as to whether or not a data field of a last entry of the back-end queue is completely filled. In response to a determination that the data field of the last entry of the back-end queue is not completely filled, another determination is made as to whether or not an address for a store instruction in a subsequent entry is equal to an address for a store instruction in the last entry plus a byte count in the last entry.

Abstract: A method for dynamically translating bus address within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system has a multiple of buses connected in a hierarchial manner. Information concerning a bus and a device attached to a bus are stored in a Hardware Namespace. In response to a request for an access to a device attached to one of the buses for the first time, a determination is made from the Hardware Namespace as to whether or not there is resource available for the device in a parent bus of the device. If there is resource available in the parent bus for the device, another determination is made from the Hardware Namespace as to whether or not the resource is exclusively allocated in the parent bus for the device. If the resource is exclusively allocated in the parent bus for the device, the device is configured according to the available resource.

Abstract: A method and system for expanding the load capabilities of a bus, such as the PCI bus. The system includes a primary bus, a plurality of secondary buses for connecting additional devices, a plurality of in-line switches, an arbiter, and control logic means. The plurality of in-line switches are used for connecting the primary bus to a corresponding one of the secondary buses, each one of the switches having an enable line for receiving a signal to enable or disable the switch. The arbiter is used for receiving requests for control of the primary bus, and for selecting one of the requests as a master for the control. The control logic means is used for enabling and disabling each of the switches, via the corresponding enable line, for connection or disconnection to the primary bus.

Abstract: A method of correcting an erroneous bit field in a cache used by a processor is disclosed. A first array stores a plurality of bit fields, respectively connected to error checking circuits, and a substitute bit field is supplied for a bit field in the first array that is found to be erroneous by the error checking circuits, the substitute bit field being read from a second array which redundantly stores the bit fields. The error checking circuits can be connected to a parity error control unit which reads the substitute bit field from the second array. The parity error control unit forces the cache into a busy mode when any of the error checking circuits indicates that a bit field is erroneous, and maintains the busy mode until the substitute bit field is supplied.

Abstract: An enhanced PCI bus architecture utilizing differential signaling is supported by an adapter slot connector providing differential signaling pins and a make-before-break connection between bus conductors and dummy loads for each bus conductor, enabling higher frequency and higher bandwidth operation. The dummy loads simulate the signal load of an adapter inserted into the slot. The PCI bus conductors are automatically disconnected from the dummy loads and connected to the adapter pins when an adapter is inserted into the slot. A balanced load bus is thus provided regardless of whether adapter slots are populated or empty.

Abstract: A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a rename register file that can be used in whole or in part for retaining cache lines from previously executed load instructions. The rename register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

Abstract: An improved method and system for accessing the most recent version of a requested data file that has been downloaded into a private network from a source external to the private network. The objects of the method and system are achieved as is now described. A network of computers is defined as private relative to one or more other networks of computers. More than one computer within said defined private network is specified as composing a "common cache." A copy of any data file entering the defined private network from a source external to the defined private network is cached at one or more computers which compose the defined "common cache." In response to a request from a computer within the defined private network for a specific data file which originates from a source external to the defined private network, a determination is made as to whether a copy of the requested specific data file is resident within the defined "common cache.

Abstract: According to the present invention, an apparatus for arbitrating between several competing requests that has a number of components cooperate together is disclosed. A number of arbiter cells are provided. These arbiter cells contain a device for shifting a token value, a number of receptors for receiving request signals, and internal circuitry for selecting one of the request signals. The request signal selected by a given arbiter cell depends on the state of the request signals being received by the cell and the position of the cell's token. Also, one or more group arbiters are provided. These group arbiters contain a device for shifting a token value, a number of receptors for receiving request signals, and internal circuitry for selecting an arbiter cell. The arbiter cell eventually selected by a given group arbiter depends on the state of the request signals being received by the arbiter and the position of the arbiter's token.

Abstract: A method of controlling a plurality of on-chip capacitors used to enhance power supply to logic circuits for a computer processor. The capacitors are each provided with transistors which temporarily disable the capacitors when an appropriate logic state is applied to the gate of the transistors. In this manner the effects of the capacitors upon system performance can be measured, and if a particular capacitor (or capacitor bank) is defective or presents an adverse impact, it can be permanently disabled by blowing fuses provided for each capacitor (or capacitor bank). The capacitors may be selectively disabled using a control circuit which has a multiplexer provided with a set of inputs from a register which contains a bit pattern that is used to determine which capacitors to disable. The register can be loaded with any pattern or with a pattern that corresponds to the states of the unblown fuses. Alternatively, all of the capacitors may be disabled, such as during power-on reset.