Abstract: A method, apparatus, and article of manufacture directing a computer system, having at least a processor, memory, and touchscreen, to create at least two virtual pointing devices. The method includes the steps of detecting at least two hands placed on the touchscreen, determining if pre-defined characteristics exist for each hand based on the shape of each hand, if pre-defined characteristics exist for each hand, creating a virtual pointing device under at least a portion of each hand in accordance with the pre-defined characteristics, and if pre-defined characteristics do not exist for at least one of the hands, creating a generic virtual pointing device under at least a portion of the hand or a unique pointing device.

Abstract: A computer system, article of manufacture, and method direct a computer system, having at least a processor, memory, and touchscreen, to create a virtual pointing device. The method includes the steps of detecting a hand placed on the touchscreen creating a virtual pointing device on the touchscreen under at least a first portion of the hand, wherein at least a first area of the virtual pointing device is assigned a command, in response to activating the first area of the virtual pointing device, executing the command, and in response to movement of at least a second portion of the first portion of the hand, redefining the command.

Abstract: A method and system for simultaneous retrieval of snoop address information in conjunction with the retrieval/storing of a cache line load/store operation. The method and system are implemented in a data processing system comprising at least one processor having an integrated controller, a cache external to the at least one processor, and an interface between the at least one processor and the external cache. The external cache includes a tag array and a data array. Standard synchronous static Random Access Memory (RAM) is used for the tag array, while synchronous burst made static RAM is used for the data array. The interface includes a shared address bus, a load address connection and an increment address connection. A cache line load/store operation is executed by placing an address for the operation on the shared address bus, and latching the address with the external cache using a signal from the load address connection.

Abstract: A method and apparatus for verifying memory coherency of a simulated computer system. A verification logic unit is used for detecting the issuance of load and store instructions from the simulated system. Targets (registers or memory locations) representing the detected instructions are then stored in queues, and marked (colored) as not having been executed. After a detected instruction has been executed and completed, the corresponding target in the queue is marked as being completed. During every clock cycle of the apparatus, the verification logic unit monitors the queues for entries (Targets) marked as completed, which are then discarded.

Abstract: A method and apparatus for providing a distributed implementation of an interrupt delivery controller in a multi-processor environment while maintaining compliance with the OpenPIC specification. Specifically, an interrupt delivery controller is maintained for each one of the central processing units. Whenever one of the central processing units resets its corresponding interrupt delivery controller, logic is used to select it as the primary interrupt controller. The primary interrupt controller coordinates the resetting of the secondary interrupt controller(s) and interrupt source units so that virtually an unlimited number of interrupt source units can be used in the system.

Abstract: Data sets of sequential data strings at a particular point in time are assigned to processing elements of a multiprocessor system at high speed and processing is executed efficiently in parallel. A mechanism for preventing allocation due to all-read to a cache block which has not yet been referred from another cache is added by providing a reference bit with respect to cache blocks. The reference bit becomes 0 when new data is read to the cache block and becomes 1 when the cache block is referenced by a CPU. In the case of reading data from another cache, if a block corresponding thereto can be replaced without the need to be written back to the other cache and the reference bit is 1, data is fetched to the shared cache memory.

Abstract: A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a cache register file, indexed via the offset field of the load instruction, for retaining cache lines from previously executed load instructions. The cache register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.

Abstract: An improved system for converting a binary floating-point number to a decimal representation within a table-based computer is disclosed. In accordance with a preferred embodiment of the present invention, a computer system is provided which includes a first table and a second table. Both of the tables have several entry locations, and each of these entry locations contains a number. The computer system also has an extraction routine for extracting a first index into the first table from a binary floating-point number, an acquiring routine for obtaining a second index into the second table from the number contained within an entry location of the first table referenced by the first index, and an identifying routine for identifying a selected entry location of the second table.

Abstract: A method and apparatus for determining the availability of a workstation in a distributed network. Availability is determined using an Availability Measurement System having a Downtime unit, an Availability Disable unit, and a Calculation unit. During the initialization of the workstation, a heartbeat monitor daemon is created to store, at predetermined time intervals, timestamps of the network. Once the workstation becomes unavailable, the recording of the timestamps ceases, thus, allowing an accurate representation of when the workstation became unavailable. Upon the return of the workstation to the status of available, the Downtime unit reads the current time of the network and the stored timestamp to calculate the duration of the unavailability of the workstation. The duration is then stored for later calculation of availability of the workstation for a defined interval of time using the Calculation unit.

Abstract: An apparatus, method, and memory direct a computer system, having at least a processor, memory, and touchscreen, to create multiple, moveable virtual pointing devices. The method includes the steps of detecting at least two hands placed on the touchscreen, creating a virtual pointing device under at least a portion of each hand positioned on the touchscreen, in response to detecting a first hand no longer being positioned on the touchscreen, determining if at least one of the other hands is no longer being positioned on the touchscreen, and in response to two or more of the hands not concurrently being positioned on the touchscreen and detecting at least one of the hands being re-positioned on the touchscreen, determining which virtual pointing device belongs to the re-positioned hand.

Abstract: An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application-level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First, a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler.

Abstract: A large number of frequent events may be accurately counted by employing a shift register. The values of several bit positions within the shift register are logically combined to generate an input to the shift register. The input is shifted in to alter the register contents whenever an event to be counted occurs. The bit positions for generating the input are selected to produce the longest sequence of nonrepeating patterns possible. The event counter may be implemented in a small area, allowing a large number of event counters to be implemented in an array like structure within a single device and to operate as extremely high frequencies.

Abstract: A browser extension method and system for a Web browser in a computer network having a client connectable to one or more servers, the client having an interface for displaying a first hypertext document with one or more hypertext links to a second hypertext document located at a server. Initially, an access parameter indicating a selected parameter which describes an access to another hypertext document is associated with a hypertext link. Thereafter, the hypertext link to the second hypertext document is selected in response to user input. Next, an access time period is initiated, during which the hypertext link accesses the second hypertext document, in response to the selection of the hypertext document. Thereafter, the access parameter is displayed in response to initiating the access time period, permitting a user to review the access parameter.

Abstract: A method and apparatus for detecting the presence/absence of adapter cards such as memory modules and alike. The method and apparatus utilize adapter cards which have wrap around pins for coupling grounds thereto. This coupled ground is then used by a Ground Detection Circuit and combined with different signals emanating from the memory modules such that when one or more of the adapter cards are absent, a default value resulting from the absence of ground is used to indicate the missing adapter(s).

Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).

Abstract: A method and apparatus in a data processing system having a plurality of node controllers and a memory unit for each of the node controllers. Each one of the node controllers including at least one processor having a cache. Each memory unit including a plurality of entries each having an exclusive bit, an address tag, and an inclusion field. Each bit of the inclusion field representing one of the node controllers. The method and apparatus allow error recovery for errors occurring within the entries without using the ECC implementation. Specifically, two parity bits are used for detecting errors within an entry and logic for flushing any cache lines represented by the entry in error. The method and apparatus also includes means for detecting persistent errors and for indicating whether the error is generated by either hardware or software.

Abstract: A cache coherence network for transferring coherence messages between processor caches in a multiprocessor data processing system is provided. The network includes a plurality of processor caches associated with a plurality of processors, and a binary logic tree circuit which can separately adapt each branch of the tree from a broadcast configuration during low levels of coherence traffic to a ring configuration during high levels of coherence traffic. A cache snoop-in input receives coherence messages and a snoop-out output outputs, at the most, one coherence message per current cycle of the network timing. A forward signal on a forward output indicates that the associated cache is outputting a message on snoop-out during the current cycle. A cache outputs received messages in a queue on the snoop-out output, after determining any response message based on the received message. The binary logic tree circuit has a plurality of binary nodes connected in a binary tree structure.

Abstract: A computer implemented method, computer system, and article of manufacture embodying computer readable program means direct a computer system to create in a window an insertion bar for inserting hierarchical level identifiers into any hierarchically arranged data. The method includes the first step of inserting a blank line at the location of an insert event, in response to detecting the insert event at the location in the window. The second event includes the step of counting a number of hierarchical levels above the blank line and placing a marker on the blank line, each marker corresponding to a horizontal position of each hierarchical level, thereby creating the insertion bar. The third step includes the step of in response to detecting a move event over one of the markers in the insertion bar, creating an additional hierarchical level identifier of the same hierarchical level and in succession to the hierarchical level corresponding to the selected marker.

Abstract: A computer system and arbitrator prevent a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Specification 2.0. The system includes an arbitrator for masking from the PCI bridge a request (REQ.sub.--) generated by a device on a second bus. The arbitrator requests that the host bus bridge flush all existing I/O requests (FLUSHREQ.sub.--) and postpone any future I/O requests from a central processing unit. The third step includes, in response to a notification from the host bus bridge that all I/O requests have been flushed and that any future I/O requests from the central processing unit will be postponed (MEMACK.sub.--), the arbitrator unmasks the request to the PCI bridge (GREQ.sub.--). In response to unmasking the request to the PCI bridge, the PCI bridge grants control of the second bus to the device (GNT.sub.--).

Abstract: A PCI local processing system is operated at 50 MHz using 5 V connectors for add-in boards and a 5 V signaling environment with an appropriate timing budget. Only the 5 V add-in boards may be used for 50 MHz adapters installed in the bus. The bus is backward compatible with existing 33 MHz PCI specifications and operates at 33 MHz if a 33 MHz adapter is installed, and will operate at 50 MHz if only 50 MHz adapters and/or 66 MHz adapters which utilize the universal boards are installed.