Abstract: A compensation circuit 10 is disclosed herein. The circuit includes a control circuit 14 including a delay element 18 with a delay sensitive to at least one parameter which causes variations in delay and also comprises a compensated driver circuit 16. The compensated driver circuit 16 has a control input B coupled to the control circuit 14 and a signal input C coupled to an input circuit 12. The delay of an output signal OUT of the compensated driver circuit 16 is controlled in part by the control circuit 14 which modifies the delay of the output signal OUT in response to variation of the parameter. Other systems and methods and numerous variations are also disclosed.

Abstract: A remote control access system uses a transmitter and a receiver. The transmitter generates an encrypted identification code which the receiver decrypts and grants access to the system if the decrypted code matches an identification code stored in the receiver. The encryption occurs by taking a 40 bit identification code and forming 5 bytes (8 bytes each). The 5 bytes are logic exclusive OR'd to form a 5 byte wide encrypted code. Decryption occurs by performing the opposite exclusive OR operation on the 5 byte wide encrypted code to convert it back to the 5 byte identification code. The 4 most significant bytes of the decrypted code are compared against the 4 most significant bytes of the previous stored decrypted code in the receiver. If the comparison yields a zero, this means the least significant byte will be within 2.sup.8 or 256 of each other and access will be granted.

Abstract: The invention is a single piece deep downset exposed lead frame (10) that can be used in current production processes. A single lead frame (10) has a die mount pad (12) that is formed with a downset or cavity into which the semiconductor die (20) is mounted. Wings (14, 15, 17, 18) lock the die pad in the device package (21) and increase the length of potential moisture paths (34a). The downset die pad (12) provides direct thermal contact of the die mount pad (12) to an external heat sink, eliminating the need for a heat slug internal to the package. The exposed die pad (12) can also be used as an RF ground connection to an RF circuit ground plane.

Abstract: A removable tab process whereby tabs (7) are affixed to the pads (3) by initially having the bonding surface as flat as possible so that bonding pressures from pad to pad are relatively uniform. Bonding is performed with the pressure applied to the pads being such that the tabs can later be easily removed without damage to the die pads, yet sufficiently strong so that the tabs do not come loose during burn in and testing. A bond strength pull between about 5 and about 40 grams per pad is appropriate for this purpose. The tabs are removed by placing the tested die (1) and attached tabs in a fixture (11) and providing a tool (31) dimensioned and moved along a path (13, 15, 17, 19) whereby each of the tabs is serially removed with the pressure applied to each tab to provide removal being preferably no greater than 40 grams.

Abstract: A hybrid leadframe-over-chip (LOC) semiconductor package is generally comprised of bonding finger elements located over a surface of a semiconductor component and electrically coupled, by means of conducting wires, to the bonding pads located on the surface. In addition, at least one bonding finger is located outside the boundary of the surface of the semiconductor component. Each bonding finger located outside the boundary is coupled, by a conducting wire, to a bonding pad positioned within the boundary of the semiconductor component. In this manner, for a given semiconductor component size and for given routing and lead dimension constraints, a larger number of conducting paths can be provided between the leadframe and the semiconductor component.

Abstract: An electrostatic decontamination method and decontamination device (10) is disclosed for decontaminating the surface of a semiconductor substrate. The decontamination device (10) includes particle ionizing device (24) that charges contaminating particles (26) on the surface of semiconductor substrate (16) thereby creating ionized particles. Decontamination device (10) also includes substrate biasing device (12) for creating a charge accumulation layer (14) at the top of semiconductor substrate (16) so that the charge accumulation layer (14) has the same charge sign as the ionized particles. In addition, the invention analytically characterizes particles using contaminating particle isolator (44) which contains a particle ionizing device (24) that charges contaminating particles (26) on the surface of semiconductor substrate (16) thereby creating ionized particles.

Abstract: A light beam is passed through a tube containing a material being monitored and a contaminant wherein the light is absorbed by the contaminant or some form of the contaminant to the exclusion of the material being monitored. Since the amount of light passing through the tube is a function of the amount of contaminant in the tube, the amount of light detected at the downstream end of the tube is a function of the amount of contaminant in the material being monitored. The detected light can be used to provide a quantitative indication of the contaminant, to provide an alarm, to shut down the system to which the material being monitored is being delivered or for other purposes. When the material being monitored is HCl gas and the contaminant is moisture, the tube will generally be stainless steel to avoid galvanic effects since the remainder of the pipe system is generally also stainless steel and the light frequency will be from about 1.0 to about 2.

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: A hybrid thermal detector (10, 110) includes a focal plane array (20, 120), a thermal isolation structure (40, 140), and an integrated circuit substrate (60, 160). The focal plane array (20, 120) includes thermal sensors (30, 130). The thermal isolation structure (40, 140) includes untrimmed mesa-type formations (44, 146, 148) and mesa strip conductors (42, 142, 144) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120) when mounted on the integrated circuit substrate (60, 160). Hybrid thermal detector (10) includes a common electrode (28) which provides a bias voltage to all thermal sensors (30). Hybrid thermal detector (110) has electrically isolated thermal sensors (130), each thermal sensor (130) is supported by mesa strip conductors (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: Disclosed is a magazine for holding semiconductor devices during storage and shipping wherein a portion 22 of the magazine is cut to form a tab 28 which is pushed through an opening 29 in a wall 23 of said magazine to block the end of the magazine, preventing semiconductor devices from falling out of said magazine.

Abstract: photosensor device (41) having tapered photodiodes (53, 55) that are interdigitated and which is compatible with typical ASIC, CMOS and BiCMOS processes. A left side photodiode array of tapered regions (53) of a first conductivity type is disposed into an epitaxial layer of a second conductivity type. This array of photodiodes is coupled together and further coupled to a first output terminal (43). A fight side photodiode array of tapered regions (55) of said first conductivity type is disposed into the epitaxial layer of the second conductivity type, spaced apart from the left side photodiode by a minimum distance. A second output terminal is coupled to the array of fight side photodiodes (51). An incident light spot (39) is focused onto the sensor. The amount of current generated at the first and second output terminals (43, 51) will be proportional to the area of the left photodiode array and the area of the fight photodiode array which is receiving light.

Abstract: A new signal quantization scheme is proposed which reduces fluctuation of the output signal by a signal quantizer (10) providing a quantized output signal and multiplying (18) said input signal X by a factor (1-w.sub.1)and finding a difference signal .DELTA..sub.in (11) between both the input signal and the previous input signal and multiplying (16) that by a weighting factor w.sub.2 from a control (13). The previous quantizer output signal Q.sub.prev is summed (17) with the weighted difference signal .DELTA..sub.in w.sub.2 and the sum is weighted by a weighting factor w.sub.1 at a multiplier (19) to yield w.sub.1 (Q.sub.prev +w.sub.2 .DELTA..sub.in). This signal is then summed at an adder (21) and applied to the quantizer (10) so that the quantizer is forced to match the fluctuation in the input signal as well as the signal itself.

Abstract: An improved electrically erasable read only memory (EEPROM) includes a EEPROM cell and a static random access memory (SRAM) cell. Complementary pairs of complementary metal oxide semiconductor (CMOS) transistors connect the gates of transistors forming the EEPROM cell to either the corresponding data nodes of the SRAM cell or to a fixed read or nonzero test voltage. When formed into an array, it is not necessary to replicate differential sense circuitry in every cell. EEPROM transistor pairs are combined into columns which share a common sense latch. The nonsero test voltage allows for measurement of the actual threshold voltages (V.sub.T) of each EEPROM device individually.

Abstract: An improved dielectric material and microcircuit having capacitive elements which employ such a dielectric material are disclosed. The dielectric material comprises polycrystalline barium strontium titanate doped with at least one donor element and having a grain size of less than 1 micron. In the preferred embodiments, the donor element may be Nb, Ta, Bi, Sb, Y, La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er or a combination thereof. The material may be further doped with an acceptor dopant to control resistivity. The microcircuit comprises capacitors having such a dielectric material and connected to a semiconductor substrate which contains embedded circuitry for reading the voltage across a capacitor.

Abstract: A preferred embodiment of this invention is a hybrid semiconductor imaging structure comprising a high speed signal conditioning substrate (e.g. Si 12) and an imaging substrate (e.g. HgCdTe 10) mounted on the conditioning substrate using an adhesive layer (e.g. epoxy 31). Infrared-sensitive time delay and integration CCD columns (14) charge coupled to sense nodes (e.g. diodes 16) are disposed in the imaging substrate. High speed signal processing channels (e.g. capacitive transimpedance amplifier 18, congelated double sampling circuit 20 and multiplexing shift register 22) are disposed in the conditioning substrate. The sense nodes are connected to the signal processing channels with low capacitance hybrid leads (e.g AI 17).

Abstract: An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.

Abstract: Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.

Abstract: A set of three cellular automata--the E-Cell, the I-Cell, and the D-Node--can be used to design and assemble parallel processing networks for such applications as signal processing and artificial intelligence. The E-Cell (FIG. 1a) is an excitory cell. The I-Cell (FIG. 2a) is an inhibitory cell. The D-Node (FIG. 3) is a combination of E-Cells and I-Cells. The use of the cellular automata is illustrated in three exemplary applications: a lateral inhibition network (FIG. 5b), a tree-search network (FIG. 6b), and a graph-search network (FIG. 7e). In particular, the tree-search and graph-search networks are implemented using the same structure as the tree or graph.

Abstract: Preferred embodiments include a microstrip patch antenna (38) which also acts as the resonator for an oscillator powered by IMPATT diodes (34, 36); this forms a monolithic transmitter (30) for microwave and millimeter wave frequencies.