Abstract: An apparatus and method for assisting persons in making decisions, using a computer programmed with artificial intelligence techniques. Real world objects and events pertaining to a particular domain are represented in a knowledge base. Best choices for solving problems are made according to the application of rules, which may be applied absolutely, comparatively, by weight, or ordered, according to methods selected by the user. The invention also permits the user to select from among various decision making strategies and permits the user to observe the effects of choices in hypothetical scenarios.

Abstract: A non-volatile counter memory is provided by using a gray code scale to store counter values in a plurality of counter memories (34) comprising a counter memory group (38). Each counter memory comprises a plurality of units which store a gray coded value. The weighting of the units is changed after a predetermined number of write operations such that the number of bit transitions is spread out among the units.

Abstract: Assembly line balancer groups tasks of multi-sided, mixed model assembly lines on the basis of per side and per model constraints. Resulting compound tasks involve less computational time and power in balancing the line.

Abstract: A speaker voice verification system uses temporal decorrelation linear transformation and includes a collector for receiving speech inputs from an unknown speaker claiming a specific identity, a word-level speech features calculator operable to use a temporal decorrelation linear transformation for generating word-level speech feature vectors from such speech inputs, word-level speech feature storage for storing word-level speech feature vectors known to belong to a speaker with the specific identity, a word-level speech feature vectors received from the unknown speaker with those received from the word-level speech feature storage, and speaker verification decision circuitry for determining, based on the similarity score, whether the unknown speaker's identity is the same as that claimed. The word-level vector scorer further includes concatenation circuitry as well as a word-specific orthogonalizing linear transformer. Other systems and methods are also disclosed.

Abstract: A register circuit and method which allows a multi-bit register to change states until such time as a particular dedicated bit is activated. Once the dedicated bit is turned to the logical on-state none of the bits, including the dedicated bit, can be changed until a reset signal is sensed.

Abstract: The degree of wire sweep and wire clearance over the buss bars in the 16 Mega Bit LOC package is found to be dependent on the angle of the bond wires. A positive wire angle range of 5 to 15 degrees is recommended for minimum wire sweep and maximum wire clearance over the buss bars. This is so because they offer the least resistance to the flow of the mold compound during transfer molding. A staggered gating system ensures that the wire angles in all cavities are positive with respect to the gate. This invention is also applicable to conventional packages.

Abstract: A method and apparatus for recovering the resolution lost when the FPA FLIR receiver scans the image at a first predetermined frequency to avoid flicker on moving objects. The input image contains 960 lines of coarse resolution data and the output field requires 480 lines of fine resolution data. The processor delays the sampling of the even numbered channels so that these samples occur between the samples taken by the odd numbered channels. The output circuit combines the signals from the odd numbered and even numbered channels which appear on two separate input lines thereto into one interleaved output on an output line. Since the detector elements overlap by 50 percent, the resulting data has increased horizontal resolution at the expense of a slight vertical distortion. More specifically, the processor combines an even numbered line with the odd numbered line thereabove in the first field and with the odd numbered line therebelow in the second field to increase vertical resolution.

Abstract: A pupil/image reversal prism (FIG. 2) forms a pupil at an image location. Such a prism has specific applicability in a DCR scheme for a thermal imaging system (FIG. 3a, 31 and 32) in which a passive DCR source is implemented by a pupil imager that forms a pupil onto the image of a thermal scene, thereby providing scene-average radiation to a thermal detector array. The pupil/image reversal prism including an input reflective surface (A), an output reflective surface (B), a positive reflective surface (C) and an intermediate folding reflective surface (D). The reflective surfaces A and B use total internal reflection to provide both transmissive and reflective operation.

Abstract: A PFC controller (FIG. 5) provides power factor correction and peak current limiting for a switch-mode power converter of any topology (buck, boost or buck-boost), without having to directly sense inductor current. The PFC control technique involves using a piecewise-polynomial analog computer (AC) to compute power transistor on-times in accordance with separate polynomial transfer functions for power-factor control and peak-current-linking using as inputs current representations of line input voltage (VLN), load output voltage (VLD), and long-term current demand (VCD). A conduction cycle is initiated by sensing when the rate of change in the inductor current reaches zero using an auxiliary winding on the current storage inductor (Wzd), and terminated after the computed on-time to implement either power-factor control or peak-current-limiting.

Abstract: A CCD imager cell (36, 38) is formed at a face of a semiconductor substrate (10) and has first (36) and second (38) phase regions. A first clocked well (14) is provided for receiving charge integrated in the first phase region (36). A second clocked well (16) is provided for receiving charge integrated in a second phase region (38) adjacent the first phase region (36). A first gate (20) is insulatively disposed over the first clocked well (14), and a second gate (22) is insulatively disposed over the second clocked well (16). A controller controls .phi..sub.1 and .phi..sub.2 pulses such that the charge is transferred from a selected one of the first and second clocked wells (14, 16) to the other, thus integrating all of the charge in the cell into one clocked well thereof. This unified charge is then transferred out from clocked well to clocked well.

Abstract: A process and structure for resolving the divergent etching requirements of a relatively thick base oxide (62) and a relatively thin gate oxide (64) in a BiCMOS integrated circuit. The necessity of etching base oxide (62) is eliminated by extending nitride mask (58) over the extrinsic base region (86) so that the relatively thick base oxide (62) only covers intrinsic base region (60) and tab region (61). Base oxide (62) at tab region (61) is partially etched in the course of forming sidewall oxide filaments (78), resulting in the residual tab oxide (62'). An extrinsic base implant is performed in extrinsic base region (86) and tab region (61), with the presence of residual tab oxide (62') affecting the profile of the implant so that it is stepped. The resulting structure, after an anneal, is extrinsic base (87'), an intrinsic base (63) (formed prior to the extrinsic base implant), and an overlap region (88') common to both.

Abstract: A circuit for the Class-A differential amplification of two input signals.A first constant current source 22 is connected between a voltage supply terminal 3 and a node 8. A second constant current source 24 is connected between the supply terminal 3 and a node 9. A first transistor T1, with a control electrode connected to input terminal 1, has a conduction path connected between node 8 and a voltage supply terminal 10. A second transistor T2, with a control electrode connected to input terminal 2, has a conduction path connected between node 9 and terminal 10. A third transistor T3, with a control electrode connected to input terminal 1, has a conduction path connected between node 9 and an output terminal 6. Finally, a fourth transistor T4, with a control electrode connected to input terminal 2, has a conduction path connected between node 8 and an output terminal 7.

Abstract: There is disclosed a temperature compensated reference voltage generation circuit and method adapted to maintain a specific temperature/voltage relationship. The circuit is designed such that it can easily be adapted to switch between different voltage temperature requirements simply by adjusting the parameters of a few circuit elements. The circuit relies upon three different current generators, each performing a different function.

Abstract: An output circuit is provided which contains voltage control circuitry (14) which drives the gates of the output transistors (18, 20) such that the change in current remains relatively constant. The desired voltage output of the voltage control circuitry (14) can be implemented for a CMOS device using N channel and P channel transistors having their gates connected to V.sub.cc and ground respectively. The amount of current control may be adjusted to compensate for environmental conditions such as temperature or voltage supply either dynamically or prior to use.

Abstract: Methods and circuits of integrated DMOS, CMOS, NPN, and PNP devices include self-aligned DMOS (411) with increased breakdown voltage and ruggedness for recovery from transients including additional Zener diodes (402/474).

Abstract: A voice coil actuated wire tensioner is used on a wire bonder in conjunction with a primary wire clamp to provide accurate control of the bond wire and looping of the bond wire between ball bonding of one end of a bond wire and stitch bonding of the other end of the bond wire.

Abstract: An elastic buffer for absorbing frequency jitter or drift of an incoming data signal which includes a serial stack of data registers. These data registers are used for storing data bits from an incoming data stream one at a time with each bit adjacent a next earlier bit at a frequency equal to the frequency of the incoming data and also for releasing stored bits onto an output data line. The stored bits are released one at a time at a predetermined fixed rate equal to the average frequency of incoming data from a number of registers away from the register into which data is being written which depends on the frequency difference between incoming data and the fixed rate aforesaid.

Abstract: A charge pump comprises high voltage and low voltage supply rails coupled to first and second capacitors via switching circuitry. The switching circuitry is operable to charge the first and second capacitors to desired voltages to generate a desired output voltage of increased magnitude.

Abstract: A threshold detection circuit (10) is provided which comprises an input node (12) and an output node (14). The input node (12) is coupled to a current mirror (22) through a resistor (32). The current mirror (22) is further coupled to another current mirror (16), which is arranged to receive a reference current proportional to absolute temperature. The reference current is mirrored and, having been increased by a multiplier is received by a current sink (28). When the voltage level at the input node (12) exceeds a predetermined voltage threshold level, the current exceeding the amount sinkable by the current sink (28) is directed to the base of a switching transistor (30) coupled to the output node (14), and produces an output voltage level at the output node (14) indicative of the threshold voltage level being reached an/or exceeded at the input node (12). The predetermined threshold voltage may be at a level exceeding the circuit supply voltage level and is independent of ambient operating temperature.