Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Abstract: An output circuit (15) includes an output transistor (16) driving a load (18) a phase 1 turn-off circuit (32), and a phase 2 turn-off circuit (34). A status circuit (28) is connected to both the phase 1 turn-off circuit (32) and the phase 2 turn-off circuit (34). Phase 1 turn-off circuit (32) and phase 2 turn-off circuit (34) provide a two phase turn-off when status circuit (28) identifies that output transistor (16) should be turned off which allows output transistor (16) to dissipate the energy stored in any inductance without output transistor (16) entering breakdown, therefore improving the circuit's (15) reliability and reducing both the energy and the increase of current in the output transistor (16).

Abstract: This invention is a silicon bipolar integrated circuit comprising: a high barrier Schottky diode clamp on a bipolar transistor, the diode clamp comprising a self-aligned PtSi layer on a silicon surface; and a TiN local interconnect partially overlying the PtSi layer. It also is a method of manufacturing an integrated circuit comprising: forming a self-aligned PtSi layer on the adjacent base and collector silicon regions, the PtSi serving as a clamp diode on the bipolar transistor; and forming an etch-patterned TiN layer partially overlying the PtSi layer, the etch-patterned TiN layer serving as local interconnects.

Abstract: Circuitry and a method are provided for selectively switching a negative voltage (-V.sub.nn) to portions of CMOS integrated circuits, which circuitry comprises a switching/decoding matrix. The switching/decoding matrix comprises a control and decode logic (CDL) which controls signal VPPENABLE to control a positive charge pump (PCP) producing positive voltage (+V.sub.pp) and which further controls signal VNNENABLE to control a negative charge pump (NCP) producing said negative voltage (-V.sub.nn). The switching/decoding matrix further comprises, for each line to be switched, a switching module which comprises a PMOS transistor (PS) having its source connected to said line and its drain connected to receive said negative voltage (-V.sub.nn) produced by said negative charge pump (NCP). The PMOS transistor (PS) gate is driven by a drive circuit being in turn driven by said control and decode logic (CDL) and connected so as to receive the positive voltage (+V.sub.pp) provided by said positive charge pump (PCP).

Abstract: An electronic learning device (10) uses keys (12a-d) which self-generate an electric signals responsive to a key being pressed. One signal drives the CORRECT segments (18b) of a display (18) and the other signal selectively drive the IN segments (18a) responsive to switching circuitry (16). Cards (14) provide a query and a plurality of possible answers, each possible answer associated with one of the keys (12a-d). A correct answer is encoded on the card.

Abstract: A First In First Out shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A read address ring counter (36) and write address ring counter (32) are responsive to respective read and write pulses to sequentially perform memory read and write operations. A comparator (40) compares the address outputs of the ring counters (36, 32) for equality. A read and a write signal generator (80, 60) are provided for producing respective read and write pulses in response to input transitions of read and write commands. A last operation R/W flip-flop (70) maintains an account of the last read and write memory operation processed by the system.

Abstract: An extremely small minimum scaled Metal-Oxide-Semiconductor, MOS, transistor is manufactured by forming a trench in a semiconductor substrate, forming a gate in the trench, and then forming source and drain regions. The source and drain regions may be diffused into the semiconductor substrate and annealed to drive the diffusions around the trench corners, thus forming the transistor channel. This improves punchthrough resistance of the transistor while yielding an extremely small gate channel. The diffusion concentration will be larger near the surface of the semiconductor substrate and smaller near the plane of the gate channel underneath the trench bottom. The trench corners have the effect of serving as a line source of dopant for diffusion under the trench such that the doping profile is the same along a radius of a cylindrical junction, thus keeping the minimum diffusion separation at the channel surface.

Abstract: A power transistor having an epitaxial layer within an isolation region is formed in a semiconductor substrate. A buried diffusion within the substrate with vertical diffusions contacting it form the isolation region. A drain, source, gate, and drift region are formed within the epitaxial layer such that a RESURF LDMOS transistor is formed having its source isolated from the substrate. Multiple power transistors may share the buried isolation region. A P type semiconductor substrate allows the power transistor and high performance CMOS circuitry to be formed on the same semiconductor die.

Abstract: A transistor (10) having a gate region formed with a thin oxide layer (28) over the gate (24). The gate (24) has a polysilicon spacer (34) formed adjacent to the gate (24) for increasing the resistance to channel hot-electron-induced degradation.

Abstract: A sequential memory (10) includes synchronous write control circuitry (26) and synchronous read control circuitry (22). The synchronous write control circuitry produces an Input Ready (IR) signal synchronous with the WRTCLK signal. The synchronous read control circuitry (22) generates a Output Ready (OR) signal synchronously with the RDCLK signal. A RSAM (read sense amplifier) signal is provided to read the sense amplifier associated with a memory (12) responsive to the RDCLK if a RAMRDY signal indicates that a read from this location may be requested on the next clock cycle.

Abstract: An interface for use with a multiprocessor computer system, having a host processor system and a graphics processor system. The interface permits extended functions to be developed on the host system or on another system, and subsequently loaded to the graphics processor system. The interface comprises software residing on both the host system side and the graphics system side, which operates at run time to permit the function to be called from a main program running on the host. The function's arguments are passed to the graphics system so that the function is executed by the graphics processor.

Abstract: A device and method for calibrating at least one temperature sensor is disclosed herein. A wafer (30) is provided having a first plurality of calibration islands (36) of a material having a melting point in the range 150.degree.-1150.degree. C. The effective reflectivity of the wafer is measured in operation using the temperature sensor or via a separate light source. A first step change in an output signal of the temperature sensor corresponding to a wafer temperature equal to the melting point of the first calibration islands is detected. Finally, the temperature sensor calibration parameters are calculated.

Abstract: A method of processing a semiconductor wafer using a wafer chuck having a first end with a non-planar surface, the non-planar surface shaped such that a wafer supported at a plurality of points about its periphery will have a uniform pressure between its surface and the non-planar surface, and pressing a surface of the wafer against the non-planar surface of the wafer chuck.

Abstract: Sound signal generator, comprising a housing (1,2) containing a microcontroller for the storage and control of reproduction of several sound messages, and a loudspeaker for reproducing the said sound messages connected to the in lieu thereof microcontroller. The housing of the sound-signal generator also carries, over at least a portion of its outer wall, a keyboard associated with the microcontroller and formed by selection keys (3) respectively bearing identification symbols for the sound messages stored in the microcontroller.

Abstract: A curved apparatus which remains stable when placed on a substantially flat surface is shown which has a base portion with an arcuately shaped back surface capable of resting on the substantially flat surface, a hinge rotatably fixed to the base portion, and a cover secured to the hinge and rotatable therewith, to prevent rocking of the base portion when the base portion's front surface is touched while the base portion is resting on the substantially flat surface. Other devices and systems are also disclosed.

Abstract: A method for manufacturing a semiconductor device, which has the steps of connecting adjacent outer leads, with an insulating photoresist or prepeg material with a width locally provided only in areas with said width along the direction of arrangement of outer leads, and of resin-sealing areas other than said outer leads and said insulating material while preventing the outflow of sealing resin by way of said insulating photoresist or prepeg material.

Abstract: A voltage regulation circuit for use in "H" bridge circuit applications utilizes feedback networks to provide analog voltage regulation of the output nodes during switching of inductive loads. The regulation of the ouptut nodes during switching of inductive loads eliminates substrate current injection.

Abstract: A single-mask self-aligned process is disclosed for formation of n and p wells for advanced CMOS and BiCMOS technologies. The proposed process forms n-well and p-well regions using a single microlithography masking step along with a selective semiconductor (Si or GeSi) growth SSG process without producing surface topography or degrading device surface planarity. This simple process ensures uniform and repeatable NMOS and PMOS gate patterning due to flat surface topography. The n-to-p well placement and spacing is self-aligned due to the use of a disposable SSG hard mask.

Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.

Abstract: The use of trimethylarsine in place of tertiary butyl arsine for low pressure organometallic vapor phase epitaxy of GaAs:C to enhance the carbon doping efficiency of CCl.sub.4. The hole concentration is three times higher with trimethylarsine then with tertiary butyl arsine in the layer grown under similar conditions. As a result, higher growth temperatures can be used with trimethyl arsine, yielding more stable carbon doping. Annealing at 650.degree. C. for 5 minutes does not degrade the trimethyl arsine-grown layers while the tertiary butyl arsine-grown layer shows decreases in both hole concentration and mobility. Also a high level of hydrogen atoms is detected in tertiary butyl arsine-grown GaAs:C. The hydrogen level is about 30 times lower in the layers grown with trimethyl arsine. The reduced hydrogen concentration is an added advantage of using trimethyl arsine since hydrogen is known to neutralize acceptors in GaAs to reduce the carrier concentrations.