Abstract: An adapter for modifying graphics software programs at load time. The invention is a process, which may be part of a hardware or firmware configuration used with a computer system, and which scans the program for selected instructions representing routines to be replaced with a substitute routine. If such an instruction is encountered, the instruction is replaced with an interrupt trap. The substitute graphics routine is located at an address stored at the interrupt trap location.

Abstract: A method of producing a cavity package around an assembled semiconductor device is disclosed. The method includes providing a chip attach pad having a plurality of chip attach pad straps, each strap extending outwardly from the outer edge of the chip attach pad and spaced about the edge of the bar pad; mounting integrated circuits having bond pads on the chip attach pad; molding a package material onto a central portion of lead fingers and the chip attach pad straps to grip and surround each lead finger with package material, with a portion of each lead finger extending externally from the ring at both the exterior and interior thereof and to secure the bar pad straps therein; electrically coupling the bond pads to the portion of desired ones of the lead fingers extending toward the interior of the ring; and enclosing both ends of the ring to provide a cavity in the ring to suspend a chip attach pad with the integrated circuit thereon within the cavity with the chip attach straps.

Abstract: Reaction gases are prevented from escaping from a reaction chamber through the use of flexible or gas seals between the interface of the reaction chamber and the junction used to connected successive reaction chambers.

Abstract: Circuitry 12 is formed at the face of a layer semiconductor 34. The circuitry includes a plurality of contact points 22 and 24. At least one anti-fuse 14 is formed in a layer vertically displaced from circuitry 12. Anti-fuse 14 is operable to selectively connect together certain ones of said contact points 22 and 24.

Abstract: An enclosed plating wheel system includes a fixed mounted shaft, feed and return spargers mounted on the shaft, and a plating wheel rotates around the fixed mounted spargers as a result of a lead frame strip being pulled around the plating wheel. A belt is also rotated around a portion of the plating wheel assembly over the lead frame strip to contain the plating solution within the plating wheel assembly.

Abstract: The present invention relates generally to single instruction, multiple data processors. More particularly, the invention relates to processors having a one dimensional array of processing elements, that finds particular application in digital signal processing such as Improved Definition Television (IDTV). Additionally, the invention relates to improvements to the processors, television and video systems and other systems improvements and methods of their operation and control.

Abstract: Field Effect Transistors are used to replace mechanical relays and to minimize the distance a Device Under Test (DUT) must drive a signal path to the receiver, to minimize insertion losses in critical paths to the DUT, and generally increase reliability in integrated test systems by eliminating the need for relays to test integrated circuits.

Abstract: A set of event qualified test protocols for use in testing integrated circuits is disclosed. A boundary scan architecture for use in the integrated circuit (10) comprises input and output test registers (12,22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal indicating a matching condition has been met. The EQM receives additional signals which indicate which testing protocol of the possible protocols is selected. The EQM (30) may control the input and output test registers (12,22) to perform a variety of tests on the incoming and outgoing data. During testing, the internal logic (20) may continue to operate at speed, thereby allowing the test circuitry to detect faults which would not otherwise be observable. A memory buffer (64) may be included to store a plurality of input data for test data. A set of standard protocols is disclosed which allows interoperability between EQMs on multiple IC's in a circuit.

Abstract: An etch process for etching copper layers that is useable in integrated circuit fabrication is disclosed which utilizes organic and amine radicals to react with copper, preferrable using photoenergizing and photodirecting assistance of high intensity ultraviolet light, to produce a product which is either volatile or easily removed in solution. The process is anisotropic.

Abstract: A charge detection amplifier embodying the invention comprises a first amplification stage (Q10-Q15) coupled to an input terminal 70 and having an output node 72. Capacitive feedback is provided by a capacitor 82 coupled between an input node 71 and said output node 72. The operating bias point of said first amplification stage is set by a first balance circuit (Q16/Q17) coupled between said output node 72 and two internal nodes 74,76 of said first amplification stage, the magnitude of said coupling being controlled by a voltage applied to a first balance circuit input terminal 84. A first buffer stage 200 is provided to couple said output node 72 to a circuit output terminal 92 and to provide adequate current to drive an external load connected to said output terminal 92. A reset switch (Q24/Q25) is provided to short circuit said capacitor 82 in response to a signal applied to a reset terminal 104.

Abstract: A translator circuit 82 and operation thereof is disclosed including a control signal generator 48 and an ECL output buffer circuit 84. Control signal generator 48 includes a CMOS inverter comprising transistors 52 and 54. The CMOS inverter is connected to a bipolar junction transistor (BJT) 70 which is further connected to as BJT 76. BJT 70 provides a voltage control signal, V.sub.CS, to ECL output buffer circuit 84. BJT 76 is connected as a transistor in a differential pair comprising transistors 76 and 86. An ECL output signal, V.sub.OUT, is generated in accordance with the operational state of transistors 76 and 86 and additional circuitry associated therewith.

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: A lead frame locater is used to locate actual positions of lead frame leads in respect to the semiconductor chip to provide accurate wire bonding of the semiconductor chip to the lead frame leads.

Abstract: There is disclosed a system and method for demodulating an analog signal using digital conversion of the analog signal. In one embodiment the incoming modulated signal is digitally sampled and a calculation is made as to both the short term and long term energy of the digitized version of the analog signal. The deviation between the short and long term energy levels is used to determine the amount of modulation of the incoming analog signal. An analog demodulated signal is then reconstructed from the digitized deviation calculations. In an alternate embodiment, a digital signal processor is used to derive the demodulated signal.

Abstract: A microwave oscillator circuit having an antenna, wherein the effective reactive impedance of the oscillator circuit is altered by the movement of a reactive impedance changing element past the antenna to cause change of the oscillation condition of the oscillator. A change in oscillation condition is sensed and sent to a utilization device to determine speed and/or position. The utilization device can be a computer which receives a signal from a wheel speed determining system, wherefrom a signal is sent back to a braking system for the wheel to control braking thereof. This can be accomplished individually for each of the four wheels to provide an anti-locking braking system.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: A BiCMOS static random access memory is disclosed, where the sense amplifiers each consist of a pair of bipolar transistors connected in emitter-coupled fashion. A pair of current sources, such as MOS transistors, are connected between the bases of said bipolar transistors and ground, to provide additional pull-down current for the bit lines. This additional pull-down current reduces the differential bit line voltage, improving the speed at which subsequent reads may be performed. Another embodiment uses a dummy column as a detection circuit, with the output of the dummy column controlling an operational amplifier, so that the operational amplifier may bias the current source pair to control the pull-down current, and thus the differential bit line voltage. Another embodiment controls the current source pair responsive to the row address, so that the effects of series bit line resistance may be taken into account in establishing the desired pull-down current.

Abstract: This is a vertical MOSFET device with low gate to source overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24, 26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, a gate electrode 36 surrounding the vertical pillar, and an insulating spacer 38 between the source 24, 26 and a portion of the gate 36 regions.

Abstract: A self-aligned bipolar structure for use on SOI (silicon on insulator) substrates is described. This structure does not require etching poly and stopping on single crystal silicon. This is also a process of forming a MOS transistor and a vertical, fully self-aligned bipolar transistor on an insulating substrate.

Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.